 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Advanced Information ANALOG PERIPHERALS - 10-Bit ADC * Up to 200 ksps * Up to 17 or 13 External Single-Ended or Differential * * * Inputs VREF from External Pin, Internal Reference, or VDD Built-in Temperature Sensor External Conversion Start Input C8051F320/1 Full Speed USB, 16K ISP FLASH MCU Family HIGH SPEED 8051 C Core - Pipelined Instruction Architecture; Executes 70% of Instructions in 1 or 2 System Clocks - ON-CHIP DEBUG - On-Chip Debug Circuitry Facilitates Full Speed, - Operation Integrated Clock Recovery; No External Crystal Required for Full Speed or Low Speed Supports Eight Flexible Endpoints 1k Byte USB Buffer Memory Integrated Transceiver; No External Resistors Required Non-Intrusive In-System Debug (No Emulator Required!) Provides Breakpoints, Single Stepping, Inspect/Modify Memory and Registers Superior Performance to Emulation Systems Using ICE-Chips, Target Pods, and Sockets - CLOCK SOURCES - Internal Oscillator: 0.25% Accuracy with Clock Recovery enabled. Supports all USB and UART Modes External Oscillator: Crystal, RC, C, or Clock (1 or 2 Pin Modes) Can Switch Between Clock Sources on-the-fly; Useful in Power Saving Strategies VOLTAGE REGULATOR INPUT: 4.0V TO 5.25V ED CROSSBAR ANALOG PERIPHERALS IN + + - FO VREG PACKAGES - 32-pin LQFP (C8051F320) - 28-pin MLP (C8051F321) TEMPERATURE RANGE: -40C TO +85C VA NC A M U X 10-bit 200ksps ADC TEMP SENSOR VREF PRECISION INTERNAL OSCILLATOR AD HIGH-SPEED CONTROLLER CORE 16KB ISP FLASH 16 INTERRUPTS 8051 CPU (25MIPS) DEBUG CIRCUITRY 2304 B SRAM POR WDT DS010-0.9 NOV02 CYGNAL Integrated Products, Inc. (c) 2002 RM AT DIGITAL I/O UART SPI SMBus PCA Timer 0 Timer 1 Timer 2 Timer 3 Port 0 Port 1 Port 2 Port 3 - Two Comparators - Internal Voltage Reference - POR/Brown-Out Detector USB FUNCTION CONTROLLER - USB Specification 2.0 Compliant - Full Speed (12 Mbps) or Low Speed (1.5 Mbps) Sectors DIGITAL PERIPHERALS - 25/21 Port I/O; All 5 V tolerant with High Sink Current - Hardware Enhanced SPITM, Enhanced UART, and SMBusTM Serial Ports Four General Purpose 16-Bit Counter/Timers 16-Bit Programmable Counter Array (PCA) with Five Capture/Compare Modules Real Time Clock Mode using External Clock Source and PCA or Timer USB Controller / Transceiver IO - Up to 25 MIPS Throughput with 25 MHz Clock - Expanded Interrupt Handler MEMORY - 2304 Bytes Internal RAM (1k + 256 + 1k USB FIFO) - 16k Bytes FLASH; In-system programmable in 512-byte N Page 1 C8051F320/1 Advanced Information Notes AD VA NC Page 2 ED IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM AT IO N Advanced Information TABLE OF CONTENTS C8051F320/1 1. SYSTEM OVERVIEW .........................................................................................................17 1.1. CIP-51TM Microcontroller Core ......................................................................................20 1.1.1. Fully 8051 Compatible ..........................................................................................20 1.1.2. Improved Throughput ............................................................................................20 1.1.3. Additional Features................................................................................................21 1.2. On-Chip Memory ............................................................................................................22 1.3. Universal Serial Bus Controller.......................................................................................23 1.4. Voltage Regulator............................................................................................................23 1.5. On-Chip Debug Circuitry ................................................................................................24 1.6. Programmable Digital I/O and Crossbar .........................................................................25 1.7. Serial Ports.......................................................................................................................25 1.8. Programmable Counter Array .........................................................................................26 1.9. 10-Bit Analog to Digital Converter.................................................................................27 1.10.Comparators ....................................................................................................................28 2. ABSOLUTE MAXIMUM RATINGS ..................................................................................29 3. GLOBAL DC ELECTRICAL CHARACTERISTICS ......................................................30 4. PINOUT AND PACKAGE DEFINITIONS........................................................................31 5. 10-BIT ADC (ADC0) .............................................................................................................39 5.1. Analog Multiplexer .........................................................................................................40 5.2. Temperature Sensor.........................................................................................................41 5.3. Modes of Operation.........................................................................................................42 5.3.1. Starting a Conversion.............................................................................................42 5.3.2. Tracking Modes .....................................................................................................43 5.3.3. Settling Time Requirements ..................................................................................44 5.4. Programmable Window Detector ....................................................................................50 5.4.1. Window Detector In Single-Ended Mode .............................................................52 5.4.2. Window Detector In Differential Mode.................................................................53 6. VOLTAGE REFERENCE....................................................................................................55 7. COMPARATORS ................................................................................................................57 8. VOLTAGE REGULATOR (REG0) ....................................................................................67 8.1. Regulator Mode Selection ...............................................................................................67 8.2. VBUS Detection..............................................................................................................67 9. CIP-51 MICROCONTROLLER .........................................................................................71 9.1. Instruction Set..................................................................................................................73 9.1.1. Instruction and CPU Timing..................................................................................73 9.1.2. MOVX Instruction and Program Memory.............................................................73 9.2. Memory Organization .....................................................................................................77 9.2.1. Program Memory ...................................................................................................77 9.2.2. Data Memory .........................................................................................................78 9.2.3. General Purpose Registers .....................................................................................78 9.2.4. Bit Addressable Locations .....................................................................................78 9.2.5. Stack ...................................................................................................................78 9.2.6. Special Function Registers.....................................................................................79 (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED IN FO RM AT IO N Page 3 C8051F320/1 Advanced Information 9.2.7. Register Descriptions .............................................................................................82 9.3. Interrupt Handler .............................................................................................................85 9.3.1. MCU Interrupt Sources and Vectors .....................................................................85 9.3.2. External Interrupts .................................................................................................86 9.3.3. Interrupt Priorities..................................................................................................86 9.3.4. Interrupt Latency....................................................................................................86 9.3.5. Interrupt Register Descriptions ..............................................................................88 9.4. Power Management Modes .............................................................................................94 9.4.1. Idle Mode ...............................................................................................................94 9.4.2. Stop Mode..............................................................................................................94 10. RESET SOURCES ..............................................................................................................97 10.1.Power-On Reset...............................................................................................................98 10.2.Power-Fail Reset / VDD Monitor....................................................................................99 10.3.External Reset................................................................................................................100 10.4.Missing Clock Detector Reset .......................................................................................100 10.5.Comparator0 Reset ........................................................................................................100 10.6.PCA Watchdog Timer Reset .........................................................................................100 10.7.FLASH Error Reset .......................................................................................................100 10.8.Software Reset...............................................................................................................101 10.9.USB Reset .....................................................................................................................101 11. FLASH MEMORY ............................................................................................................105 11.1.Programming The FLASH Memory .............................................................................105 11.1.1. FLASH Lock and Key Functions ........................................................................105 11.1.2. FLASH Erase Procedure......................................................................................105 11.1.3. FLASH Write Procedure .....................................................................................106 11.2.Non-volatile Data Storage .............................................................................................107 11.3.Security Options ............................................................................................................107 12. EXTERNAL RAM .............................................................................................................111 12.1.Accessing User XRAM .................................................................................................111 12.2.Accessing USB FIFO Space..........................................................................................112 13. OSCILLATORS...................................................................................................................115 13.1.Programmable Internal Oscillator .................................................................................115 13.1.1. Programming the Internal Oscillator on C8051F320/1 Devices .........................116 13.1.2. Internal Oscillator Suspend Mode .......................................................................116 13.2.External Oscillator Drive Circuit...................................................................................118 13.2.1. Clocking Timers Directly Through the External Oscillator ................................118 13.2.2. External Crystal Example ....................................................................................118 13.2.3. External RC Example ..........................................................................................119 13.2.4. External Capacitor Example ................................................................................119 13.3.4x Clock Multiplier .......................................................................................................121 13.4.System and USB Clock Selection .................................................................................122 13.4.1. System Clock Selection .......................................................................................122 13.4.2. USB Clock Selection ...........................................................................................122 14. PORT INPUT/OUTPUT ...................................................................................................125 14.1.Priority Crossbar Decoder .............................................................................................127 AD VA NC Page 4 ED IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM AT IO N Advanced Information C8051F320/1 14.2.Port I/O Initialization.....................................................................................................129 14.3.General Purpose Port I/O...............................................................................................132 15. UNIVERSAL SERIAL BUS CONTROLLER (USB0) ....................................................141 15.1.Endpoint Addressing .....................................................................................................142 15.2.USB Transceiver ...........................................................................................................142 15.3.USB Register Access.....................................................................................................144 15.4.USB Clock Configuration .............................................................................................148 15.5.FIFO Management.........................................................................................................149 15.5.1. FIFO Split Mode ..................................................................................................149 15.5.2. FIFO Double Buffering .......................................................................................149 15.5.3. FIFO Access ........................................................................................................150 15.6.Function Addressing......................................................................................................151 15.7.Function Configuration and Control .............................................................................152 15.8.Interrupts .......................................................................................................................155 15.9.The Serial Interface Engine ...........................................................................................159 15.10.Endpoint0.....................................................................................................................159 15.10.1.Endpoint0 SETUP Transactions .........................................................................160 15.10.2.Endpoint0 IN Transactions .................................................................................160 15.10.3.Endpoint0 OUT Transactions .............................................................................161 15.11.Configuring Endpoints1-3 ...........................................................................................164 15.12.Controlling Endpoints1-3 IN .......................................................................................164 15.12.1.Endpoints1-3 IN Interrupt or Bulk Mode ...........................................................164 15.12.2.Endpoints1-3 IN Isochronous Mode...................................................................165 15.13.Controlling Endpoints1-3 OUT ...................................................................................168 15.13.1.Endpoints1-3 OUT Interrupt or Bulk Mode .......................................................168 15.13.2.Endpoints1-3 OUT Isochronous Mode...............................................................168 16. SYSTEM MANAGEMENT BUS (SMBUS0) ...................................................................173 16.1.Supporting Documents ..................................................................................................174 16.2.SMBus Configuration....................................................................................................174 16.3.SMBus Operation ..........................................................................................................175 16.3.1. Arbitration............................................................................................................175 16.3.2. Clock Low Extension...........................................................................................176 16.3.3. SCL Low Timeout ...............................................................................................176 16.3.4. SCL High (SMBus Free) Timeout.......................................................................176 16.4.Using the SMBus...........................................................................................................177 16.4.1. SMBus Configuration Register............................................................................178 16.4.2. SMB0CN Control Register ..................................................................................181 16.4.3. Data Register........................................................................................................184 16.5.SMBus Transfer Modes.................................................................................................185 16.5.1. Master Transmitter Mode ....................................................................................185 16.5.2. Master Receiver Mode.........................................................................................186 16.5.3. Slave Receiver Mode ...........................................................................................187 16.5.4. Slave Transmitter Mode.......................................................................................188 16.6.SMBus Status Decoding................................................................................................189 17. UART0 .................................................................................................................................191 (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED IN FO RM AT IO N Page 5 C8051F320/1 Advanced Information 17.1.Enhanced Baud Rate Generation...................................................................................192 17.2.Operational Modes ........................................................................................................193 17.2.1. 8-Bit UART .........................................................................................................193 17.2.2. 9-Bit UART .........................................................................................................194 17.3.Multiprocessor Communications...................................................................................195 18. ENHANCED SERIAL PERIPHERAL INTERFACE (SPI0) .........................................201 18.1.Signal Descriptions........................................................................................................202 18.1.1. Master Out, Slave In (MOSI) ..............................................................................202 18.1.2. Master In, Slave Out (MISO) ..............................................................................202 18.1.3. Serial Clock (SCK) ..............................................................................................202 18.1.4. Slave Select (NSS)...............................................................................................202 18.2.SPI0 Master Mode Operation........................................................................................203 18.3.SPI0 Slave Mode Operation ..........................................................................................205 18.4.SPI0 Interrupt Sources...................................................................................................206 18.5.Serial Clock Timing ......................................................................................................207 18.6.SPI Special Function Registers .....................................................................................208 19. TIMERS ...............................................................................................................................215 19.1.Timer 0 and Timer 1......................................................................................................215 19.1.1. Mode 0: 13-bit Counter/Timer.............................................................................215 19.1.2. Mode 1: 16-bit Counter/Timer.............................................................................216 19.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload.................................................217 19.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) ...........................................218 19.2.Timer 2 .......................................................................................................................223 19.2.1. 16-bit Timer with Auto-Reload ...........................................................................223 19.2.2. 8-bit Timers with Auto-Reload............................................................................224 19.2.3. USB Start-of-Frame Capture ...............................................................................225 19.3.Timer 3 .......................................................................................................................228 19.3.1. 16-bit Timer with Auto-Reload ...........................................................................228 19.3.2. 8-bit Timers with Auto-Reload............................................................................229 19.3.3. USB Start-of-Frame Capture ...............................................................................230 20. PROGRAMMABLE COUNTER ARRAY (PCA0) .........................................................233 20.1.PCA Counter/Timer.......................................................................................................234 20.2.Capture/Compare Modules............................................................................................235 20.2.1. Edge-triggered Capture Mode .............................................................................236 20.2.2. Software Timer (Compare) Mode........................................................................237 20.2.3. High Speed Output Mode ....................................................................................238 20.2.4. Frequency Output Mode ......................................................................................239 20.2.5. 8-Bit Pulse Width Modulator Mode ....................................................................240 20.2.6. 16-Bit Pulse Width Modulator Mode ..................................................................241 20.3.Watchdog Timer Mode..................................................................................................242 20.3.1. Watchdog Timer Operation .................................................................................242 20.3.2. Watchdog Timer Usage .......................................................................................243 20.4.Register Descriptions for PCA ......................................................................................244 21. C2 INTERFACE .................................................................................................................249 21.1.C2 Interface Registers ...................................................................................................249 AD VA NC Page 6 ED IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM AT IO N Advanced Information C8051F320/1 21.2.C2 Pin Sharing...............................................................................................................251 (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED IN FO RM AT Page 7 IO N C8051F320/1 Advanced Information Notes AD VA NC Page 8 ED IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM AT IO N Advanced Information LIST OF FIGURES AND TABLES C8051F320/1 22. SYSTEM OVERVIEW ........................................................................................................17 Table 22.1. Product Selection Guide .......................................................................................17 Figure 22.1. C8051F320 Block Diagram.................................................................................18 Figure 22.2. C8051F321 Block Diagram.................................................................................19 Figure 22.3. Comparison of Peak MCU Execution Speeds.....................................................20 Figure 22.4. On-Chip Clock and Reset....................................................................................21 Figure 22.5. On-Board Memory Map ......................................................................................22 Figure 22.6. USB Controller Block Diagram ..........................................................................23 Figure 22.7. Development/In-System Debug Diagram ...........................................................24 Figure 22.8. Digital Crossbar Diagram....................................................................................25 Figure 22.9. PCA Block Diagram............................................................................................26 Figure 22.10. PCA Block Diagram..........................................................................................26 Figure 22.11. 10-Bit ADC Block Diagram..............................................................................27 Figure 22.12. Comparator0 Block Diagram ............................................................................28 23. ABSOLUTE MAXIMUM RATINGS .................................................................................29 Table 23.1. Absolute Maximum Ratings* ...............................................................................29 24. GLOBAL DC ELECTRICAL CHARACTERISTICS .....................................................30 Table 24.1. Global DC Electrical Characteristics....................................................................30 25. PINOUT AND PACKAGE DEFINITIONS .......................................................................31 Table 25.1. Pin Definitions for the C8051F320/1 ...................................................................31 Figure 25.1. LQFP-32 Pinout Diagram (Top View)................................................................34 Figure 25.2. LQFP-32 Package Diagram.................................................................................35 Table 25.2. LQFP-32 Package Dimensions.............................................................................35 Figure 25.3. MLP-28 Pinout Diagram (Top View) .................................................................36 Figure 25.4. MLP-28 Package Drawing ..................................................................................37 Table 25.3. MLP-28 Package Dimensions ..............................................................................37 26. 10-BIT ADC (ADC0) ............................................................................................................39 Figure 26.1. ADC0 Functional Block Diagram .......................................................................39 Figure 26.2. Typical Temperature Sensor Transfer Function..................................................41 Figure 26.3. 10-Bit ADC Track and Conversion Example Timing.........................................43 Figure 26.4. ADC0 Equivalent Input Circuits .........................................................................44 Figure 26.5. AMX0P: AMUX0 Positive Channel Select Register..........................................45 Figure 26.6. AMX0N: AMUX0 Negative Channel Select Register........................................46 Figure 26.7. ADC0CF: ADC0 Configuration Register ...........................................................47 Figure 26.8. ADC0H: ADC0 Data Word MSB Register.........................................................47 Figure 26.9. ADC0L: ADC0 Data Word LSB Register ..........................................................48 Figure 26.10. ADC0CN: ADC0 Control Register ...................................................................49 Figure 26.11. ADC0GTH: ADC0 Greater-Than Data High Byte Register.............................50 Figure 26.12. ADC0GTL: ADC0 Greater-Than Data Low Byte Register ..............................50 Figure 26.13. ADC0LTH: ADC0 Less-Than Data High Byte Register ..................................51 Figure 26.14. ADC0LTL: ADC0 Less-Than Data Low Byte Register ...................................51 Figure 26.15. ADC Window Compare Example: Right-Justified Single-Ended Data............52 Figure 26.16. ADC Window Compare Example: Left-Justified Single-Ended Data ..............52 (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED IN FO RM AT IO N Page 9 C8051F320/1 Advanced Information Figure 26.17. ADC Window Compare Example: Right-Justified Differential Data...............53 Figure 26.18. ADC Window Compare Example: Left-Justified Differential Data .................53 Table 26.1. ADC0 Electrical Characteristics...........................................................................54 27. VOLTAGE REFERENCE ...................................................................................................55 Figure 27.1. Voltage Reference Functional Block Diagram ...................................................55 Figure 27.2. REF0CN: Reference Control Register ................................................................56 Table 27.1. Voltage Reference Electrical Characteristics .......................................................56 28. COMPARATORS ...............................................................................................................57 Figure 28.1. Comparator0 Functional Block Diagram ............................................................57 Figure 28.2. Comparator1 Functional Block Diagram ............................................................58 Figure 28.3. Comparator Hysteresis Plot.................................................................................59 Figure 28.4. CPT0CN: Comparator0 Control Register ...........................................................60 Figure 28.5. CPT0MX: Comparator0 MUX Selection Register .............................................61 Figure 28.6. CPT0MD: Comparator0 Mode Selection Register .............................................62 Figure 28.7. CPT1CN: Comparator1 Control Register ...........................................................63 Figure 28.8. CPT1MX: Comparator1 MUX Selection Register .............................................64 Figure 28.9. CPT1MD: Comparator1 Mode Selection Register .............................................65 Table 28.1. Comparator Electrical Characteristics ..................................................................66 29. VOLTAGE REGULATOR (REG0) ...................................................................................67 Table 29.1. Voltage Regulator Electrical Specifications .........................................................67 Figure 29.1. REG0 Configuration: USB Bus-Powered ...........................................................68 Figure 29.2. REG0 Configuration: USB Self-Powered...........................................................68 Figure 29.3. REG0 Configuration: USB Self-Powered, Regulator Disabled ..........................69 Figure 29.4. REG0 Configuration: No USB Connection ........................................................69 Figure 29.5. REG0CN: Voltage Regulator Control.................................................................70 30. CIP-51 MICROCONTROLLER ........................................................................................71 Figure 30.1. CIP-51 Block Diagram ........................................................................................71 Table 30.1. CIP-51 Instruction Set Summary..........................................................................73 Figure 30.2. Memory Map .......................................................................................................77 Table 30.2. Special Function Register (SFR) Memory Map ...................................................79 Table 30.3. Special Function Registers ...................................................................................79 Figure 30.3. DPL: Data Pointer Low Byte ..............................................................................82 Figure 30.4. DPH: Data Pointer High Byte .............................................................................82 Figure 30.5. SP: Stack Pointer .................................................................................................83 Figure 30.6. PSW: Program Status Word ................................................................................83 Figure 30.7. ACC: Accumulator..............................................................................................84 Figure 30.8. B: B Register .......................................................................................................84 Table 30.4. Interrupt Summary................................................................................................87 Figure 30.9. IE: Interrupt Enable .............................................................................................88 Figure 30.10. IP: Interrupt Priority ..........................................................................................89 Figure 30.11. EIE1: Extended Interrupt Enable 1 ...................................................................90 Figure 30.12. EIP1: Extended Interrupt Priority 1...................................................................91 Figure 30.13. EIE2: Extended Interrupt Enable 2 ...................................................................92 Figure 30.14. EIP2: Extended Interrupt Priority 2...................................................................92 Figure 30.15. IT01CF: INT0/INT1 Configuration Register ....................................................93 AD VA NC Page 10 ED IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM AT IO N Advanced Information C8051F320/1 Figure 30.16. PCON: Power Control Register ........................................................................95 31. RESET SOURCES .............................................................................................................97 Figure 31.1. Reset Sources ......................................................................................................97 Figure 31.2. Power-On and VDD Monitor Reset Timing .......................................................98 Figure 31.3. VDM0CN: VDD Monitor Control ......................................................................99 Figure 31.4. RSTSRC: Reset Source Register.......................................................................102 Table 31.1. Reset Electrical Characteristics ..........................................................................103 32. FLASH MEMORY ...........................................................................................................105 Table 32.1. FLASH Electrical Characteristics.......................................................................106 Figure 32.1. FLASH Program Memory Map and Security Byte...........................................108 Figure 32.2. PSCTL: Program Store R/W Control ................................................................108 Figure 32.3. FLKEY: FLASH Lock and Key Register .........................................................109 Figure 32.4. FLSCL: FLASH Scale Register ........................................................................109 33. EXTERNAL RAM ............................................................................................................111 Figure 33.1. External Ram Memory Map..............................................................................111 Figure 33.2. XRAM Memory Map Expanded View .............................................................112 Figure 33.3. EMI0CN: External Memory Interface Control .................................................113 34. OSCILLATORS ..................................................................................................................115 Figure 34.1. Oscillator Diagram ............................................................................................115 Figure 34.2. OSCICN: Internal Oscillator Control Register .................................................117 Figure 34.3. OSCICL: Internal Oscillator Calibration Register ............................................117 Figure 34.4. OSCXCN: External Oscillator Control Register...............................................120 Figure 34.5. CLKMUL: Clock Multiplier Control Register..................................................121 Table 34.1. Typical USB Full Speed Clock Settings.............................................................122 Table 34.2. Typical USB Low Speed Clock Settings............................................................122 Figure 34.6. CLKSEL: Clock Select Register .......................................................................123 Table 34.3. Oscillator Electrical Characteristics ...................................................................124 35. PORT INPUT/OUTPUT ..................................................................................................125 Figure 35.1. Port I/O Functional Block Diagram ..................................................................125 Figure 35.2. Port I/O Cell Block Diagram.............................................................................126 Figure 35.3. Crossbar Priority Decoder with No Pins Skipped .............................................127 Figure 35.4. Crossbar Priority Decoder with Crystal Pins Skipped ......................................128 Figure 35.5. XBR0: Port I/O Crossbar Register 0 .................................................................130 Figure 35.6. XBR1: Port I/O Crossbar Register 1 .................................................................131 Figure 35.7. P0: Port0 Register..............................................................................................133 Figure 35.8. P0MDIN: Port0 Input Mode Register ...............................................................133 Figure 35.9. P0MDOUT: Port0 Output Mode Register.........................................................134 Figure 35.10. P0SKIP: Port0 Skip Register...........................................................................134 Figure 35.11. P1: Port1 Register............................................................................................135 Figure 35.12. P1MDIN: Port1 Input Mode Register .............................................................135 Figure 35.13. P1MDOUT: Port1 Output Mode Register.......................................................136 Figure 35.14. P1SKIP: Port1 Skip Register...........................................................................136 Figure 35.15. P2: Port2 Register............................................................................................137 Figure 35.16. P2MDIN: Port2 Input Mode Register .............................................................137 Figure 35.17. P2MDOUT: Port2 Output Mode Register.......................................................138 (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED IN FO RM AT IO N Page 11 C8051F320/1 Advanced Information Figure 35.18. P2SKIP: Port2 Skip Register...........................................................................138 Figure 35.19. P3: Port3 Register............................................................................................139 Figure 35.20. P3MDIN: Port3 Input Mode Register .............................................................139 Figure 35.21. P3MDOUT: Port3 Output Mode Register.......................................................140 Table 35.1. Port I/O DC Electrical Characteristics................................................................140 36. UNIVERSAL SERIAL BUS CONTROLLER (USB0) ...................................................141 Figure 36.1. USB0 Block Diagram........................................................................................141 Table 36.1. Endpoint Addressing Scheme.............................................................................142 Figure 36.2. USB0XCN: USB0 Transceiver Control............................................................143 Figure 36.3. USB0 Register Access Scheme .........................................................................144 Figure 36.4. USB0ADR: USB0 Indirect Address Register ...................................................145 Figure 36.5. USB0DAT: USB0 Data Register ......................................................................146 Figure 36.6. INDEX: USB0 Endpoint Index (USB Register) ...............................................146 Table 36.2. USB0 Controller Registers .................................................................................147 Figure 36.7. CLKREC: Clock Recovery Control (USB Register) ........................................148 Figure 36.8. USB FIFO Allocation........................................................................................149 Table 36.3. FIFO Configurations...........................................................................................150 Figure 36.9. FIFOn: USB0 Endpoint FIFO Access (USB Registers) ...................................150 Figure 36.10. FADDR: USB0 Function Address (USB Register) ........................................151 Figure 36.11. POWER: USB0 Power (USB Register) ..........................................................153 Figure 36.12. FRAMEL: USB0 Frame Number Low (USB Register) .................................154 Figure 36.13. FRAMEH: USB0 Frame Number High (USB Register) ................................154 Figure 36.14. IN1INT: USB0 IN Endpoint Interrupt (USB Register)...................................155 Figure 36.15. OUT1INT: USB0 Out Endpoint Interrupt (USB Register).............................156 Figure 36.16. CMINT: USB0 Common Interrupt (USB Register)........................................157 Figure 36.17. IN1IE: USB0 IN Endpoint Interrupt Enable (USB Register) .........................158 Figure 36.18. OUT1IE: USB0 Out Endpoint Interrupt Enable (USB Register)....................158 Figure 36.19. CMIE: USB0 Common Interrupt Enable (USB Register) ..............................159 Figure 36.20. E0CSR: USB0 Endpoint0 Control (USB Register) ........................................162 Figure 36.21. E0CNT: USB0 Endpoint 0 Data Count (USB Register) .................................163 Figure 36.22. EINCSRL: USB0 IN Endpoint Control High Byte (USB Register) ...............166 Figure 36.23. EINCSRH: USB0 IN Endpoint Control Low Byte (USB Register) ...............167 Figure 36.24. EOUTCSRL: USB0 OUT Endpoint Control High Byte (USB Register) .......169 Figure 36.25. EOUTCSRH: USB0 OUT Endpoint Control Low Byte (USB Register) .......170 Figure 36.26. EOUTCNTL: USB0 OUT Endpoint Count Low (USB Register) ..................170 Figure 36.27. EOUTCNTH: USB0 OUT Endpoint Count High (USB Register) .................170 Table 36.4. USB Transceiver Electrical Characteristics........................................................171 37. SYSTEM MANAGEMENT BUS (SMBUS0) ..................................................................173 Figure 37.1. SMBus Block Diagram .....................................................................................173 Figure 37.2. Typical SMBus Configuration ..........................................................................174 Figure 37.3. SMBus Transaction ...........................................................................................175 Table 37.1. SMBus Clock Source Selection..........................................................................178 Figure 37.4. Typical SMBus SCL Generation.......................................................................178 Table 37.2. Minimum SDA Setup and Hold Times ..............................................................179 Figure 37.5. SMB0CF: SMBus Clock/Configuration Register .............................................180 AD VA NC Page 12 ED IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM AT IO N Advanced Information C8051F320/1 Figure 37.6. SMB0CN: SMBus Control Register .................................................................182 Table 37.3. Sources for Hardware Changes to SMB0CN .....................................................183 Figure 37.7. SMB0DAT: SMBus Data Register ...................................................................184 Figure 37.8. Typical Master Transmitter Sequence...............................................................185 Figure 37.9. Typical Master Receiver Sequence ...................................................................186 Figure 37.10. Typical Slave Receiver Sequence ...................................................................187 Figure 37.11. Typical Slave Transmitter Sequence ...............................................................188 Table 37.4. SMBus Status Decoding .....................................................................................189 38. UART0 ................................................................................................................................191 Figure 38.1. UART0 Block Diagram.....................................................................................191 Figure 38.2. UART0 Baud Rate Logic ..................................................................................192 Figure 38.3. UART Interconnect Diagram ............................................................................193 Figure 38.4. 8-Bit UART Timing Diagram ...........................................................................193 Figure 38.5. 9-Bit UART Timing Diagram ...........................................................................194 Figure 38.6. UART Multi-Processor Mode Interconnect Diagram .......................................195 Figure 38.7. SCON0: Serial Port 0 Control Register.............................................................196 Figure 38.8. SBUF0: Serial (UART0) Port Data Buffer Register .........................................197 Table 38.1. Timer Settings for Standard Baud Rates Using The Internal Oscillator ............198 Table 38.2. Timer Settings for Standard Baud Rates Using an External Oscillator..............198 Table 38.3. Timer Settings for Standard Baud Rates Using an External Oscillator..............199 Table 38.4. Timer Settings for Standard Baud Rates Using an External Oscillator..............199 Table 38.5. Timer Settings for Standard Baud Rates Using an External Oscillator..............200 Table 38.6. Timer Settings for Standard Baud Rates Using an External Oscillator..............200 39. ENHANCED SERIAL PERIPHERAL INTERFACE (SPI0) ........................................201 Figure 39.1. SPI Block Diagram............................................................................................201 Figure 39.2. Multiple-Master Mode Connection Diagram ....................................................204 Figure 39.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram ...204 Figure 39.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram ....204 Figure 39.5. Data/Clock Timing Diagram .............................................................................207 Figure 39.6. SPI0CFG: SPI0 Configuration Register............................................................208 Figure 39.7. SPI0CN: SPI0 Control Register ........................................................................209 Figure 39.8. SPI0CKR: SPI0 Clock Rate Register ................................................................210 Figure 39.9. SPI0DAT: SPI0 Data Register ..........................................................................211 Figure 39.10. SPI Slave Timing (CKPHA = 0) .....................................................................212 Figure 39.11. SPI Slave Timing (CKPHA = 1) .....................................................................212 Figure 39.12. SPI Master Timing (CKPHA = 0) ...................................................................213 Figure 39.13. SPI Master Timing (CKPHA = 1) ...................................................................213 Table 39.1. SPI Timing Parameters .......................................................................................214 40. TIMERS ..............................................................................................................................215 Figure 40.1. T0 Mode 0 Block Diagram................................................................................216 Figure 40.2. T0 Mode 2 Block Diagram................................................................................217 Figure 40.3. T0 Mode 3 Block Diagram................................................................................218 Figure 40.4. TCON: Timer Control Register.........................................................................219 Figure 40.5. TMOD: Timer Mode Register...........................................................................220 Figure 40.6. CKCON: Clock Control Register......................................................................221 (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED IN FO RM AT IO N Page 13 C8051F320/1 Advanced Information Figure 40.7. TL0: Timer 0 Low Byte ....................................................................................222 Figure 40.8. TL1: Timer 1 Low Byte ....................................................................................222 Figure 40.9. TH0: Timer 0 High Byte ...................................................................................222 Figure 40.10. TH1: Timer 1 High Byte .................................................................................222 Figure 40.11. Timer 2 16-Bit Mode Block Diagram .............................................................223 Figure 40.12. Timer 2 8-Bit Mode Block Diagram ...............................................................224 Figure 40.13. Timer 2 SOF Capture Mode (T2SPLIT = `0') ................................................225 Figure 40.14. Timer 2 SOF Capture Mode (T2SPLIT = `1') ................................................225 Figure 40.15. TMR2CN: Timer 2 Control Register ..............................................................226 Figure 40.16. TMR2RLL: Timer 2 Reload Register Low Byte ............................................227 Figure 40.17. TMR2RLH: Timer 2 Reload Register High Byte ...........................................227 Figure 40.18. TMR2L: Timer 2 Low Byte ............................................................................227 Figure 40.19. TMR2H Timer 2 High Byte ............................................................................227 Figure 40.20. Timer 3 16-Bit Mode Block Diagram .............................................................228 Figure 40.21. Timer 3 8-Bit Mode Block Diagram ...............................................................229 Figure 40.22. Timer 3 SOF Capture Mode (T3SPLIT = `0') ................................................230 Figure 40.23. Timer 3 SOF Capture Mode (T3SPLIT = `1') ................................................230 Figure 40.24. TMR3CN: Timer 3 Control Register ..............................................................231 Figure 40.25. TMR3RLL: Timer 3 Reload Register Low Byte ............................................232 Figure 40.26. TMR3RLH: Timer 3 Reload Register High Byte ...........................................232 Figure 40.27. TMR3L: Timer 3 Low Byte ............................................................................232 Figure 40.28. TMR3H Timer 3 High Byte ............................................................................232 41. PROGRAMMABLE COUNTER ARRAY (PCA0) ........................................................233 Figure 41.1. PCA Block Diagram..........................................................................................233 Figure 41.2. PCA Counter/Timer Block Diagram .................................................................234 Table 41.1. PCA Timebase Input Options .............................................................................234 Figure 41.3. PCA Interrupt Block Diagram...........................................................................235 Table 41.2. PCA0CPM Register Settings for PCA Capture/Compare Modules ...................235 Figure 41.4. PCA Capture Mode Diagram ............................................................................236 Figure 41.5. PCA Software Timer Mode Diagram................................................................237 Figure 41.6. PCA High Speed Output Mode Diagram ..........................................................238 Figure 41.7. PCA Frequency Output Mode ...........................................................................239 Figure 41.8. PCA 8-Bit PWM Mode Diagram ......................................................................240 Figure 41.9. PCA 16-Bit PWM Mode ...................................................................................241 Figure 41.10. PCA Module 4 with Watchdog Timer Enabled ..............................................242 Table 41.3. Watchdog Timer Timeout Intervals..................................................................243 Figure 41.11. PCA0CN: PCA Control Register ....................................................................244 Figure 41.12. PCA0MD: PCA Mode Register ......................................................................245 Figure 41.13. PCA0CPMn: PCA Capture/Compare Mode Registers ...................................246 Figure 41.14. PCA0L: PCA Counter/Timer Low Byte .........................................................247 Figure 41.15. PCA0H: PCA Counter/Timer High Byte ........................................................247 Figure 41.16. PCA0CPLn: PCA Capture Module Low Byte ................................................248 Figure 41.17. PCA0CPHn: PCA Capture Module High Byte ...............................................248 42. C2 INTERFACE ................................................................................................................249 Figure 42.1. C2ADD: C2 Address Register ..........................................................................249 AD VA NC Page 14 ED IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM AT IO N Advanced Information C8051F320/1 (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED IN FO RM AT Page 15 IO N Figure 42.2. DEVICEID: C2 Device ID Register (update) ...................................................249 Figure 42.3. REVID: C2 Revision ID Register .....................................................................250 Figure 42.4. FPCTL: C2 FLASH Programming Control Register ........................................250 Figure 42.5. FPDAT: C2 FLASH Programming Data Register ............................................250 Figure 42.6. Typical C2 Pin Sharing .....................................................................................251 C8051F320/1 Advanced Information Notes AD VA NC Page 16 ED IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM AT IO N Advanced Information 1. SYSTEM OVERVIEW C8051F320/1 C8051F320/1 devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are listed below. Refer to Table 1.1 for specific product feature selection. * * * * * * * * * * * * * * * High-speed pipelined 8051-compatible microcontroller core (up to 25 MIPS) In-system, full-speed, non-intrusive debug interface (on-chip) Universal Serial Bus (USB) Function Controller with eight flexible endpoint pipes, integrated transceiver, and 1k FIFO RAM Supply Voltage Regulator (5V-to-3V) True 10-bit 200 ksps 17-channel single-ended/differential ADC with analog multiplexer On-chip Voltage Reference and Temperature Sensor On-chip Voltage Comparators (2) Precision programmable 12 MHz internal oscillator and 4x clock multiplier 16k bytes of on-chip FLASH memory 2304 total bytes of on-chip RAM (256 + 1k + 1k USB FIFO) SMBus/I2C, Enhanced UART, and Enhanced SPI serial interfaces implemented in hardware Four general-purpose 16-bit timers Programmable Counter/Timer Array (PCA) with five capture/compare modules and Watchdog Timer function On-chip Power-On Reset, VDD Monitor, and Missing Clock Detector 25/21 Port I/O (5V tolerant) Each device is specified for 2.7 V-to-3.6 V operation over the industrial temperature range (-40C to +85C). (Note that 3.0 V-to-3.6 V is required for USB communication.) The Port I/O and /RST pins are tolerant of input signals up to 5 V. C8051F320/1 are available in a 32-pin LQFP or a 28-pin MLP package. VA NC ED The on-chip Cygnal 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production MCU installed in the final application. This debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging without occupying package pins. Table 1.1. Product Selection Guide Programmable Counter Array Calibrated Internal Oscillator Supply Voltage Regulator AD IN With on-chip Power-On Reset, VDD monitor, Voltage Regulator, Watchdog Timer, and clock oscillator, C8051F320/1 devices are truly stand-alone System-on-a-Chip solutions. The FLASH memory can be reprogrammed in-circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. User software has complete control of all peripherals, and may individually shut down any or all peripherals for power savings. FO RM Timers (16-bit) AT Digital Port I/Os ! ! 25 21 ! ! IO 10-bit 200ksps ADC Temperature Sensor ! ! N Voltage Reference ! ! Analog Comparators FLASH Memory Enhanced SPI MIPS (Peak) SMBus/I2C C8051F320 C8051F321 25 25 16k 16k 2304 2304 ! ! ! ! ! ! ! ! ! ! ! ! 4 4 2 2 LQFP-32 MLP-28 (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 Page 17 Package UART RAM USB C8051F320/1 Advanced Information Figure 1.1. C8051F320 Block Diagram N P 0 5.0V REGIN OUT VDD GND Port 1 Latch UART Timer 0,1,2,3 / RTC PCA/ WDT IO C R O S S B A R CP0 Voltage IN Regulator Enable Port 0 Latch Analog/Digital Power D r v P 1 D r v P 2 D r v P 3 D r v P0.0 P0.1 P0.2/XTAL1 P0.3/XTAL2 P0.4 P0.5 P0.6/CNVSTR P0.7/VREF P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0/C2D C2D Debug HW Reset /RST/C2CK POR XTAL1 XTAL2 BrownOut 1K byte XRAM External Oscillator Circuit 12MHz Internal Oscillator x4 2 FO VREF VDD System Clock C o r SFR Bus e 2 Clock Recovery RM 8 0 5 1 16kbyte FLASH 256 byte SRAM AT SMBus SPI Port 2 Latch Port 3 Latch VREF + + Temp CP1 1,2,3,4 USB Transceiver D+ D- USB Controller IN USB Clock VBUS ED 1K byte USB SRAM 10-bit 200ksps ADC A M U X AIN0-AIN16 VDD VREF AD Page 18 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. VA NC Advanced Information C8051F320/1 Figure 1.2. C8051F321 Block Diagram P0.0 P0.1 P0.2/XTAL1 P0.3/XTAL2 P0.4 P0.5 P0.6/CNVSTR P0.7/VREF P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 5.0V REGIN Voltage IN Regulator OUT Enable VDD GND Analog/Digital Power UART Timer 0,1,2,3 / RTC PCA/ WDT IO C R O S S B A R CP0 Port 1 Latch C2D Debug HW Reset /RST/C2CK XTAL1 XTAL2 RM POR BrownOut 8 0 5 1 16kbyte FLASH 256 byte SRAM 1K byte XRAM AT SMBus SPI Port 2 Latch Port 3 Latch VREF + + Temp External Oscillator Circuit 12MHz Internal Oscillator x4 2 System Clock FO C o r SFR Bus e N D r v P 1 D r v P 2 D r v P 3 D r v CP1 Port 0 Latch P 0 P3.0/C2D 2 Clock Recovery USB Clock D+ D- USB Transceiver USB Controller IN 1,2,3,4 VREF VDD VBUS ED 1K byte USB SRAM 10-bit 200ksps ADC A M U X AIN0-AIN11 VDD VREF (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC Page 19 C8051F320/1 1.1. 1.1.1. Advanced Information CIP-51TM Microcontroller Core Fully 8051 Compatible 1.1.2. Improved Throughput The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execution time. Number of Instructions 26 50 FO Clocks to Execute 1 2 2/3 5 RM 3 3/4 7 The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute with a maximum system clock of 12-to-24 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than four system clock cycles. AT 4 3 IO 4/5 1 The C8051F320/1 family utilizes Cygnal's proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51TM instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The CIP-51 core offers all the peripherals included with a standard 8052, including four 16-bit counter/timers, a fullduplex UART with extended baud rate configuration, an enhanced SPI port, 2304 bytes of on-chip RAM, 128 byte Special Function Register (SFR) address space, and 25/21 I/O pins. N 5 2 8 1 14 Figure 1.3. Comparison of Peak MCU Execution Speeds 25 AD Page 20 VA NC 20 MIPS 15 10 5 ED Cygnal Microchip Philips ADuC812 CIP-51 PIC17C75x 80C51 8051 (25MHz clk) (33MHz clk) (33MHz clk) (16MHz clk) IN With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. Figure 1.3 shows a comparison of peak throughputs for various 8-bit microcontroller cores with their maximum system clocks. DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. Advanced Information 1.1.3. Additional Features C8051F320/1 The C8051F320/1 SoC family includes several key enhancements to the CIP-51 core and peripherals to improve performance and ease of use in end applications. The extended interrupt handler provides 16 interrupt sources into the CIP-51 (as opposed to 7 for the standard 8051), allowing numerous analog and digital peripherals to interrupt the controller. An interrupt driven system requires less intervention by the MCU, giving it more effective throughput. The extra interrupt sources are very useful when building multi-tasking, real-time systems. Nine reset sources are available: power-on reset circuitry (POR), an on-chip VDD monitor (forces reset when power supply voltage drops below VRST as given in Table 10.1 on page 103), the USB controller (USB bus reset or a VBUS transition), a Watchdog Timer, a Missing Clock Detector, a voltage level detection from Comparator0, a forced software reset, an external reset pin, and an errant FLASH read/write protection circuit. Each reset source except for the POR, Reset Input Pin, or FLASH error may be disabled by the user in software. The WDT may be permanently enabled in software after a power-on reset during MCU initialization. The internal oscillator is factory calibrated to 12 MHz 1.5%, and the internal oscillator period may be user programmed in ~0.25% increments. A clock recovery mechanism allows the internal oscillator to be used with the 4x Clock Multiplier as the USB clock source in Full Speed mode; the internal oscillator can also be used as the USB clock source in Low Speed mode. External oscillators may also be used with the 4x Clock Multiplier. An external oscillator drive circuit is also included, allowing an external crystal, ceramic resonator, capacitor, RC, or CMOS clock source to generate the system clock. The system clock may be configured to use the internal oscillator, external oscillator, or the Clock Multiplier output divided by 2. If desired, the system clock source may be switched on-the-fly between oscillator sources. An external oscillator can be extremely useful in low power applications, allowing the MCU to run from a slow (power saving) external clock source, while periodically switching to the internal oscillator as needed. Figure 1.4. On-Chip Clock and Reset ED VA NC IN VDD + - FO Supply Monitor RM Enable Power On Reset AT '0' USB Controller Enable IO (wired-OR) N Reset Funnel VBUS Transition Px.x Px.x Comparator 0 + C0RSEF /RST AD Missing Clock Detector (oneshot) EN PCA WDT Software Reset (SWRSF) EN MCD Enable Clock Multiplier System Clock XTAL1 XTAL2 External Oscillator Drive CIP-51 Microcontroller Core Extended Interrupt Handler WDT Enable Internal Oscillator Errant FLASH Operation System Reset Clock Select (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 Page 21 C8051F320/1 1.2. On-Chip Memory Advanced Information Program memory consists of 16k bytes of FLASH. This memory may be reprogrammed in-system in 512 byte sectors, and requires no special off-chip programming voltage. See Figure 1.5 for the MCU system memory map. Figure 1.5. On-Board Memory Map 0xFF 0x3E00 0x3DFF RESERVED 0x80 0x7F Upper 128 RAM (Indirect Addressing Only) (Direct and Indirect Addressing) Bit Addressable General Purpose Registers RM PROGRAM/DATA MEMORY (FLASH) DATA MEMORY (RAM) INTERNAL DATA ADDRESS SPACE Special Function Register's (Direct Addressing Only) FO AT (In-System Programmable in 512 Byte Sectors) ED IN 0xFFFF 0x0800 0x07FF 0x0400 0x03FF 0x0000 16K FLASH 0x30 0x2F 0x20 0x1F 0x00 EXTERNAL DATA ADDRESS SPACE 0x0000 VA NC Same 2048 bytes as from 0x0000 to 0x07FF, wrapped on 2K-byte boundaries USB FIFOs 1024 Bytes XRAM - 1024 Bytes (accessable using MOVX instruction) AD Page 22 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. IO N The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable as four banks of general purpose registers, and the next 16 bytes can be byte addressable or bit addressable. Lower 128 RAM (Direct and Indirect Addressing) Advanced Information 1.3. Universal Serial Bus Controller C8051F320/1 The Universal Serial Bus Controller (USB0) is a USB 2.0 compliant Full or Low Speed function with integrated transceiver and endpoint FIFO RAM. A total of eight endpoint pipes are available: a bi-directional control endpoint (Endpoint0) and three pairs of IN/OUT endpoints (Endpoints1-3 IN/OUT). A 1k block of XRAM is used as dedicated USB FIFO space. This FIFO space is distributed among Endpoints0-3; Endpoint1-3 FIFO slots can be configured as IN, OUT, or both IN and OUT (split mode). The maximum FIFO size is 512 bytes (Endpoint3). The USB Transceiver is USB 2.0 compliant, and includes on-chip matching and pull-up resistors. The pull-up resistors can be enabled/disabled in software, and will appear on the D+ or D- pin according to the software-selected speed setting (Full or Low Speed). Figure 1.6. USB Controller Block Diagram Transceiver Serial Interface Engine (SIE) Endpoint0 VDD D+ IN FO IN/OUT ED Data Transfer Control RM OUT OUT AT USB Control, Status, and Interrupt Registers USB0 can be operated as a Full or Low Speed function. On-chip 4x Clock Multiplier and clock recovery circuitry allow both Full and Low Speed options to be implemented with the on-chip precision oscillator as the USB clock source. An external oscillator source can also be used with the 4x Clock Multiplier to generate the USB clock. The CPU clock source is independent of the USB clock. IO Endpoint1 Endpoint2 IN IN IN Endpoint3 OUT D- VA NC USB FIFOs (1k RAM) 1.4. C8051F320/1 devices include a 5 V-to-3 V voltage regulator (REG0). When enabled, the REG0 output appears on the VDD pin and can be used to power external devices. REG0 can be enabled/disabled by software. (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD Voltage Regulator N CIP-51 Core Page 23 C8051F320/1 1.5. On-Chip Debug Circuitry Advanced Information The C8051F320/1 devices include on-chip Cygnal 2-Wire (C2) debug circuitry that provides non-intrusive, full speed, in-circuit debugging of the production part installed in the end application. Cygnal's debugging system supports inspection and modification of memory and registers, breakpoints, and single stepping. No additional target RAM, program memory, timers, or communications channels are required. All the digital and analog peripherals are functional and work correctly while debugging. All the peripherals (except for the USB, ADC, and SMBus) are stalled when the MCU is halted, during single stepping, or at a breakpoint in order to keep them synchronized. The C8051F310DK development kit provides all the hardware and software necessary to develop application code and perform in-circuit debugging with the C8051F320/1 MCUs. The kit includes software with a developer's studio and debugger, an integrated 8051 assembler, and an RS-232 to C2 serial adapter. It also has a target application board with the associated MCU installed and prototyping area, plus the RS-232 and C2 cables, and wall-mount power supply. The Development Kit requires a Windows 95/98/NT/ME/2000 computer with one available RS-232 serial port. As shown in Figure 1.7, the PC is connected via RS-232 to the Serial Adapter. A six-inch ribbon cable connects the Serial Adapter to the user's application board, picking up the two C2 pins and VDD and GND. The Serial Adapter takes its power from the application board. For applications where there is not sufficient power available from the target board, the provided power supply can be connected directly to the Serial Adapter. The Cygnal IDE interface is a vastly superior developing and debugging configuration, compared to standard MCU emulators that use on-board "ICE Chips" and require the MCU in the application board to be socketed. Cygnal's debug paradigm increases ease of use and preserves the performance of the precision analog peripherals. Figure 1.7. Development/In-System Debug Diagram CYGNAL Integrated Development Environment WINDOWS 95/98/NT/ME/2000 VA NC ED IN RS-232 Serial Adapter C2 (x2), VDD, GND AD VDD GND C8051F320 Page 24 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO TARGET PCB RM AT IO N Advanced Information 1.6. Programmable Digital I/O and Crossbar C8051F320/1 Figure 1.8. Digital Crossbar Diagram Priority Decoder Highest Priority UART SPI (Internal Digital Signals) SMBus CP0 Outputs CP1 Outputs SYSCLK 2 4 2 2 2 FO RM 8 8 8 1 XBR0, XBR1, PnSKIP Registers PnMDOUT, PnMDIN Registers AT P0 I/O Cells P1 I/O Cells P2 I/O Cells P3 I/O Cells The Digital Crossbar allows mapping of internal digital system resources to Port I/O pins (See Figure 1.8). On-chip counter/timers, serial buses, HW interrupts, comparator outputs, and other digital signals in the controller can be configured to appear on the Port I/O pins specified in the Crossbar Control registers. This allows the user to select the exact mix of general purpose Port I/O and digital resources needed for the particular application. IO N C8051F320 devices include 25 I/O pins (three byte-wide Ports and one 1-bit-wide Port); C8051F321 devices include 21 I/O pins (two byte-wide Ports, one 4-bit-wide Port, and one 1-bit-wide Port). The C8051F320/1 Ports behave like typical 8051 Ports with a few enhancements. Each Port pin may be configured as an analog input or a digital I/O pin. Pins selected as digital I/Os may additionally be configured for push-pull or open-drain output. The "weak pull-ups" that are fixed on typical 8051 devices may be globally disabled, providing power savings capabilities. P0.0 P0.7 P1.0 P1.7 P2.0 P2.7 P3.0 PCA Lowest Priority T0, T1 VA NC ED 6 2 8 IN Digital Crossbar Note: P2.4-P2.7 only available on the C8051F320 P0 (P0.0-P0.7) 8 (Port Latches) P1 (P1.0-P1.7) 8 P2 (P2.0-P2.7) 8 AD P3 (P3.0) 1.7. Serial Ports The C8051F320/1 Family includes an SMBus/I2C interface, a full-duplex UART with enhanced baud rate configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention. (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 Page 25 C8051F320/1 1.8. Advanced Information Programmable Counter Array SYSCLK/12 SYSCLK/4 Timer 0 Overflow ECI SYSCLK External Clock/8 PCA CLOCK MUX 16-Bit Counter/Timer Capture/Compare Module 0 ED Capture/Compare Module 1 IN Capture/Compare Module 2 Capture/Compare Module 3 FO RM CEX2 Figure 1.9. PCA Block Diagram AT CEX3 Each capture/compare module can be configured to operate in one of six modes: Edge-Triggered Capture, Software Timer, High Speed Output, 8- or 16-bit Pulse Width Modulator, or Frequency Output. Additionally, Capture/Compare Module 4 offers watchdog timer (WDT) capabilities. Following a system reset, Module 4 is configured and enabled in WDT mode. The PCA Capture/Compare Module I/O and External Clock Input may be routed to Port I/O via the Digital Crossbar. IO An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the four 16-bit general purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with five programmable capture/compare modules. The PCA clock is derived from one of six sources: the system clock divided by 12, the system clock divided by 4, Timer 0 overflows, an External Clock Input (ECI), the system clock, or the external oscillator clock source divided by 8. The external clock source selection is useful for real-time clock functionality, where the PCA is clocked by an external source while the internal oscillator drives the system clock. VA NC N Capture/Compare Module 4 / WDT CEX0 CEX1 CEX4 AD Page 26 ECI Crossbar Port I/O DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. Advanced Information 1.9. 10-Bit Analog to Digital Converter C8051F320/1 Figure 1.10. 10-Bit ADC Block Diagram Analog Multiplexer P1.0 P1.7 P2.0 P2.4-2.7 available on C8051F320 19-to-1 AMUX P2.7 P3.0 IN FO Configuration, Control, and Data Registers RM Window compare registers for the ADC data can be configured to interrupt the controller when ADC data is either within or outside of a specified range. The ADC can monitor a key voltage continuously in background mode, but not interrupt the controller unless the converted data is within/outside the specified range. AT End of Conversion Interrupt Conversions can be started in six ways: a software command, an overflow of Timer 0, 1, 2, or 3, or an external convert start signal. This flexibility allows the start of conversion to be triggered by software events, a periodic signal (timer overflows), or external HW signals. Conversion completions are indicated by a status bit and an interrupt (if enabled). The resulting 10-bit data word is latched into the ADC data SFRs upon completion of a conversion. IO Start Conversion 16 N 000 001 010 011 100 101 The C8051F320/1 devices include an on-chip 10-bit SAR ADC with a 17-channel differential input multiplexer. With a maximum throughput of 200 ksps, the ADC offers true 10-bit linearity with an INL of 1LSB. The ADC system includes a configurable analog multiplexer that selects both positive and negative ADC inputs. Ports1-3 are available as ADC inputs; additionally, the on-chip Temperature Sensor output and the power supply voltage (VDD) are available as ADC inputs. User firmware may shut down the ADC to save power. AD0BUSY (W) Timer 0 Overflow Timer 2 Overflow Timer 1 Overflow CNVSTR Input Timer 3 Overflow VDD ED Temp Sensor (+) 10-Bit SAR ADC Data Registers VA NC P1.0 (-) ADC P1.7 P2.0 P2.4-2.7 available on C8051F320 19-to-1 AMUX Window Compare Logic Window Compare Interrupt P2.7 P3.0 VREF GND (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD Page 27 C8051F320/1 1.10. Comparators Advanced Information Figure 1.11. Comparator0 Block Diagram CP0EN CP0OUT CPT0CN CP0RIF CP0FIF CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 VDD FO RM CP0 Interrupt CP0 Rising-edge CP0 Falling-edge Interrupt Logic CP0RIE CP0FIE D SET CPT0MX CMX0N1 CMX0N0 CMX0P0 P1.0 P1.4 P2.0 P2.4 CP0 + ED IN + Q D SET CMX0P1 AT Q CLR Comparator interrupts may be generated on rising, falling, or both edges. When in IDLE mode, these interrupts may be used as a "wake-up" source. Comparator0 may also be configured as a reset source. Figure 1.11 shows the Comparator0 block diagram. IO N C8051F320/1 devices include two on-chip voltage comparators that are enabled/disabled and configured via user software. Port I/O pins may be configured as comparator inputs via a selection mux. Two comparator outputs may be routed to a Port pin if desired: a latched output and/or an unlatched (asynchronous) output. Comparator response time is programmable, allowing the user to select between high-speed and low-power modes. Positive and negative hysteresis are also configurable. CP0 Crossbar GND Reset Decision Tree CLR Q Q VA NC P1.1 P1.5 P2.1 P2.5 (SYNCHRONIZER) CP0 - CP0A CPT0MD CP0RIE CP0FIE AD Page 28 Note: P2.4 and P2.5 available only on C8051F320 CP0MD1 CP0MD0 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. Advanced Information 2. ABSOLUTE MAXIMUM RATINGS C8051F320/1 Table 2.1. Absolute Maximum Ratings* Storage Temperature Voltage on any Port I/O Pin or /RST with respect to GND Voltage on VDD with respect to GND Maximum Total current through VDD and GND Maximum output current sunk by /RST or any Port pin * -65 -0.3 -0.3 IO Ambient temperature under bias -55 N PARAMETER CONDITIONS MIN TYP MAX 125 UNITS C C V V mA mA 150 5.8 4.2 500 100 (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED IN FO Note: stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. RM AT Page 29 C8051F320/1 3. Advanced Information GLOBAL DC ELECTRICAL CHARACTERISTICS Table 2.2. Global DC Electrical Characteristics PARAMETER Digital Supply Voltage Digital Supply Current with CPU active Digital Supply Current with CPU active and USB active Digital Supply Current with CPU inactive (not accessing FLASH) Digital Supply Current (suspend mode) Digital Supply Current (shutdown) Digital Supply RAM Data Retention Voltage Specified Operating Temperature Range CONDITIONS MIN 2.7 TYP 3.3 N -40C to +85C, 25 MHz System Clock unless otherwise specified. MAX 3.6 UNITS V mA mA A mA mA A mA A A A A V VDD=3.3V, Clock=25MHz VDD=3.3V, Clock=1MHz VDD=3.3V, Clock=32kHz RM -40 VDD=3.3V, Clock=25MHz VDD=3.3V, Clock=1MHz VDD=3.3V, Clock=32kHz FO Oscillator not running IN ED AT VDD=3.3V, Clock=25MHz VDD=3.3V, Clock=1MHz VDD=3.3V, Clock=32kHz IO 26 1 TBD TBD TBD TBD TBD TBD TBD TBD < 0.1 1.5 +85 C AD Page 30 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. VA NC Advanced Information 4. PINOUT AND PACKAGE DEFINITIONS C8051F320/1 Table 4.1. Pin Definitions for the C8051F320/1 Name `F320 `F321 Power In 2.7-3.6 V Power Supply Voltage Input. VDD 6 6 Type Description 3.3 V Voltage Regulator Output. See Section 8. Ground. GND /RST/ 3 3 D I/O 9 C2CK P3.0/ 10 C2D REGIN 7 9 D I/O D I/O 10 D I/O 7 Clock signal for the C2 Debug Interface. Bi-directional data signal for the C2 Debug Interface. VBUS D+ DP0.0 P0.1 P0.2/ 8 4 5 2 1 8 4 5 2 1 D In ED D I/O D I/O D I/O D I/O D I/O VA NC 32 28 XTAL1 P0.3/ A In D I/O AD 31 27 XTAL2 P0.4 P0.5 External Clock Output. This pin is the excitation driver for an A I/O or external crystal or resonator, or an external clock input for CMOS, capacitor, or RC oscillator configurations. See Section 13. D In D I/O D I/O Port 0.4. See Section 14 for a complete description. Port 0.5. See Section 14 for a complete description. 30 29 26 25 (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 IN USB D-. Power In 5 V Regulator Input. This pin is the input to the on-chip voltage regulator. VBUS Sense Input. This pin should be connected to the VBUS signal of a USB network. A 5 V signal on this pin indicates a USB network connection. USB D+. Port 0.0. See Section 14 for a complete description. Port 0.1. See Section 14 for a complete description. Port 0.2. See Section 14 for a complete description. External Clock Input. This pin is the external oscillator return for a crystal or resonator. See Section 13. Port 0.3. See Section 14 for a complete description. FO Port 3.0. See Section 14 for a complete description. RM Device Reset. Open-drain output of internal POR or VDD monitor. An external source can initiate a system reset by driving this pin low for at least 15 s. See Section 10. AT Power Out IO Page 31 N Pin Numbers C8051F320/1 Advanced Information Table 4.1. Pin Definitions for the C8051F320/1 Pin Numbers Name `F320 P0.6/ 28 CNVSTR P0.7/ 27 VREF P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 22 21 20 19 18 17 16 15 14 13 12 11 23 A I/O D I/O 24 `F321 Port 0.6. See Section 14 for a complete description. ADC0 External Convert Start Input. See Section 5. Port 0.7. See Section 14 for a complete description. External VREF input or output. See Section 6. Type Description D I/O or Port 1.0. See Section 14 for a complete description. A In D I/O or Port 1.1. See Section 14 for a complete description. A In D I/O or Port 1.2. See Section 14 for a complete description. A In D I/O or Port 1.3. See Section 14 for a complete description. A In D I/O or Port 1.5. See Section 14 for a complete description. A In AD VA NC Page 32 ED D I/O or Port 1.6. See Section 14 for a complete description. A In D I/O or Port 1.7. See Section 14 for a complete description. A In D I/O or Port 2.0. See Section 14 for a complete description. A In D I/O or Port 2.1. See Section 14 for a complete description. A In D I/O or Port 2.2. See Section 14 for a complete description. A In D I/O or Port 2.3. See Section 14 for a complete description. A In D I/O or Port 2.4. See Section 14 for a complete description. A In D I/O or Port 2.5. See Section 14 for a complete description. A In D I/O or Port 2.6. See Section 14 for a complete description. A In IN D I/O or Port 1.4. See Section 14 for a complete description. A In DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM AT IO N Advanced Information C8051F320/1 Table 4.1. Pin Definitions for the C8051F320/1 Pin Numbers Name `F320 P2.7 11 `F321 D I/O or Port 2.7. See Section 14 for a complete description. A In Type Description (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED IN FO RM AT Page 33 IO N C8051F320/1 Advanced Information Figure 4.1. LQFP-32 Pinout Diagram (Top View) P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P0.0 GND D+ DVDD REGIN VBUS 2 3 4 5 6 7 8 AT C8051F320 Top View P0.1 1 IO RM 14 15 P2.4 P2.3 P2.2 N 24 23 22 21 20 19 18 17 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 32 31 30 29 28 27 26 10 11 12 IN 13 FO ED P2.7 P2.6 /RST / C2CK P3.0 / C2D P2.5 AD VA NC Page 34 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. 16 9 25 Advanced Information C8051F320/1 Figure 4.2. LQFP-32 Package Diagram D D1 IO MIN 0.05 1.35 0.30 - N Table 4.2. LQFP-32 Package Dimensions A A1 A2 b D D1 e E E1 MM TYP 1.40 0.37 9.00 7.00 0.80 9.00 7.00 MAX 1.60 0.15 1.45 0.45 - E1 E 32 1 A2 b (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED IN FO A A1 e PIN 1 IDENTIFIER RM AT Page 35 C8051F320/1 Advanced Information Figure 4.3. MLP-28 Pinout Diagram (Top View) 28 27 26 25 24 23 GND P0.1 P0.0 GND D+ DVDD REGIN 1 2 3 4 5 6 7 AT P2.0 14 22 IO 21 20 19 18 17 16 15 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 C8051F321 Top View ED 10 11 IN GND 12 VBUS P3.0 / C2D P2.3 P2.2 /RST / C2CK P2.1 13 8 9 AD VA NC Page 36 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM P1.0 N Advanced Information Figure 4.4. MLP-28 Package Drawing C8051F320/1 Bottom View L 7 IO MIN 0.80 0 0 0.18 2.90 2.90 0.45 0.09 - N Table 4.2. MLP-28 Package Dimensions 15 A A1 A2 A3 b D D2 E E2 e L N ND NE R AA BB CC DD MM TYP 0.90 0.02 0.65 0.25 0.23 5.00 3.15 5.00 3.15 0.5 0.55 28 7 7 0.435 0.435 0.18 0.18 MAX 1.00 0.05 1.00 0.30 3.35 3.35 0.65 - 10 11 12 13 D2 D2 2 E2 R 5 4 17 18 19 20 21 2 1 DETAIL 1 28 27 26 25 24 23 E2 2 3 6xe D ED A2 AA BB DD CC A1 e Side View IN A (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC A3 DETAIL 1 22 FO RM e 6xe E AT 6 b 14 16 8 9 Page 37 C8051F320/1 Advanced Information Notes AD VA NC Page 38 ED IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM AT IO N Advanced Information 5. 10-BIT ADC (ADC0) C8051F320/1 Figure 5.1. ADC0 Functional Block Diagram AD0INT AD0BUSY AD0WINT P1.0 AMX0P AMX0P4 AMX0P3 AMX0P2 AMX0P1 AMX0P0 AT VDD AD0TM AD0EN AD0CM2 P1.7 P2.0 P2.4-2.7 available on C8051F320 19-to-1 AMUX P2.7 P3.0 VDD Temp Sensor RM (+) (-) AD0SC0 AD0LJST AD0SC4 AD0SC3 AD0SC2 AD0SC1 AD0CM1 AD0CM0 000 001 010 011 100 101 IO ADC0CN SYSCLK REF The ADC0 subsystem for the C8051F320/1 consists of two analog multiplexers (referred to collectively as AMUX0) with 17 total input selections, and a 200 ksps, 10-bit successive-approximation-register ADC with integrated trackand-hold and programmable window detector. The AMUX0, data conversion modes, and window detector are all configurable under software control via the Special Function Registers shown in Figure 5.1. ADC0 operates in both Single-ended and Differential modes, and may be configured to measure P1.0-P3.0, the Temperature Sensor output, or VDD with respect to P1.0-P3.0, VREF, or GND. The ADC0 subsystem is enabled only when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1. The ADC0 subsystem is in low power shutdown when this bit is logic 0. N ADC0H ADC0L Start Conversion FO 10-Bit SAR AD0BUSY (W) Timer 0 Overflow Timer 2 Overflow Timer 1 Overflow CNVSTR Input Timer 3 Overflow P1.0 P1.7 P2.0 P2.4-2.7 available on C8051F320 19-to-1 AMUX P2.7 P3.0 VREF GND IN ADC AD0WINT Window Compare Logic ED AMX0N AMX0N4 AMX0N3 AMX0N2 AMX0N1 AMX0N0 32 ADC0LTH ADC0LTL ADC0GTH ADC0GTL ADC0CF (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC Page 39 C8051F320/1 5.1. Analog Multiplexer Advanced Information Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be configured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for analog input, set to `0' the corresponding bit in register PnMDIN (for n = 0,1,2,3). To force the Crossbar to skip a Port pin, set to `1' the corresponding bit in register PnSKIP (for n = 0,1,2). See Section "14. Port Input/Output" on page 125 for more Port I/O configuration details. AD VA NC Input Voltage (Differential) VREF * 511/512 VREF * 256/512 0 -VREF * 256/512 - VREF Right-Justified ADC0H:ADC0L (AD0LJST = 0) 0x01FF 0x0100 0x0000 0xFF00 0xFE00 IN When in Differential Mode, conversion codes are represented as 10-bit signed 2's complement numbers. Inputs are measured from -VREF to VREF * 511/512. Example codes are shown below for both right-justified and left-justified data. For right-justified data, the unused MSBs of ADC0H are a sign-extension of the data word. For left-justified data, the unused LSBs in the ADC0L register are set to `0'. Left-Justified ADC0H:ADC0L (AD0LJST = 1) 0x7FC0 0x4000 0x0000 0xC000 0x8000 Page 40 ED DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO Input Voltage (Single-Ended) VREF * 1023/1024 VREF * 512/1024 VREF * 256/1024 0 Right-Justified ADC0H:ADC0L (AD0LJST = 0) 0x03FF 0x0200 0x0100 0x0000 Left-Justified ADC0H:ADC0L (AD0LJST = 1) 0xFFC0 0x8000 0x4000 0x0000 RM AT The conversion code format differs between Single-ended and Differential modes. The registers ADC0H and ADC0L contain the high and low bytes of the output conversion code from the ADC at the completion of each conversion. Data can be right-justified or left-justified, depending on the setting of the AD0LJST bit (ADC0CN.0). When in Single-ended Mode, conversion codes are represented as 10-bit unsigned integers. Inputs are measured from `0' to VREF * 1023/1024. Example codes are shown below for both right-justified and left-justified data. Unused bits in the ADC0H and ADC0L registers are set to `0'. IO N AMUX0 selects the positive and negative inputs to the ADC. Any of the following may be selected as the positive input: P1.0-P3.0, the on-chip temperature sensor, or the positive power supply (VDD). Any of the following may be selected as the negative input: P1.0-P3.0, VREF, or GND. When GND is selected as the negative input, ADC0 operates in Single-ended Mode; all other times, ADC0 operates in Differential Mode. The ADC0 input channels are selected in the AMX0P and AMX0N registers as described in Figure 5.5 and Figure 5.6. Advanced Information 5.2. Temperature Sensor C8051F320/1 The typical temperature sensor transfer function is shown in Figure 5.2. The output voltage (VTEMP) is the positive ADC input when the temperature sensor is selected by bits AMX0P4-0 in register AMX0P. 1000 900 800 VTEMP = 2.86(TEMPC) + 776 mV 700 600 500 -50 0 FO 50 RM 100 (Celsius) Note that parameters which affect ADC measurement, in particular the voltage reference value, will also affect temperature measurement. (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED IN AT Page 41 IO (mV) N Figure 5.2. Typical Temperature Sensor Transfer Function C8051F320/1 5.3. Modes of Operation Advanced Information 5.3.1. Starting a Conversion A conversion can be initiated in one of five ways, depending on the programmed states of the ADC0 Start of Conversion Mode bits (AD0CM2-0) in register ADC0CN. Conversions may be initiated by one of the following: 1. 2. 3. 4. 5. 6. Writing a `1' to the AD0BUSY bit of register ADC0CN A Timer 0 overflow (i.e., timed continuous conversions) A Timer 2 overflow A Timer 1 overflow A rising edge on the CNVSTR input signal (pin P0.6) A Timer 3 overflow AD VA NC Page 42 ED Important Note About Using CNVSTR: The CNVSTR input pin also functions as Port pin P0.6. When the CNVSTR input is used as the ADC0 conversion source, Port pin P0.6 should be skipped by the Digital Crossbar. To configure the Crossbar to skip P0.6, set to `1' Bit6 in register P0SKIP. See Section "14. Port Input/Output" on page 125 for details on Port I/O configuration. IN Writing a `1' to AD0BUSY provides software control of ADC0 whereby conversions are performed "on-demand". During conversion, the AD0BUSY bit is set to logic 1 and reset to logic 0 when the conversion is complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0 interrupt flag (AD0INT). Note: When polling for ADC conversion completions, the ADC0 interrupt flag (AD0INT) should be used. Converted data is available in the ADC0 data registers, ADC0H:ADC0L, when bit AD0INT is logic 1. Note that when Timer 2 or Timer 3 overflows are used as the conversion source, Low Byte overflows are used if Timer 2/3 is in 8-bit mode; High byte overflows are used if Timer 2/3 is in 16-bit mode. See Section "19. Timers" on page 215 for timer configuration. DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM AT IO N ADC0 has a maximum conversion speed of 200 ksps. The ADC0 conversion clock is a divided version of the system clock, determined by the AD0SC bits in the ADC0CF register (system clock divided by (AD0SC + 1) for 0 AD0SC 31). Advanced Information 5.3.2. Tracking Modes C8051F320/1 Figure 5.3. 10-Bit ADC Track and Conversion Example Timing A. ADC0 Timing for External Trigger Source CNVSTR (AD0CM[2:0]=100) 1 RM 2 3 4 5 6 7 8 9 6 7 8 9 AT 6 7 8 SAR Clocks Low Power or Convert FO IO 9 The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0 input is continuously tracked, except when a conversion is in progress. When the AD0TM bit is logic 1, ADC0 operates in low-power track-and-hold mode. In this mode, each conversion is preceded by a tracking period of 3 SAR clocks (after the start-of-conversion signal). When the CNVSTR signal is used to initiate conversions in low-power tracking mode, ADC0 tracks only when CNVSTR is low; conversion begins on the rising edge of CNVSTR (see Figure 5.3). Tracking can also be disabled (shutdown) when the device is in low power standby or sleep modes. Low-power trackand-hold mode is also useful when AMUX settings are frequently changed, due to the settling time requirements described in Section "5.3.3. Settling Time Requirements" on page 44. AD0TM=1 Track Convert AD0TM=0 Track or Convert IN Convert N 10 11 Low Power Mode Track VA NC Write '1' to AD0BUSY, Timer 0, Timer 2, Timer 1, Timer 3 Overflow (AD0CM[2:0]=000, 001,010 011, 101) SAR Clocks AD0TM=1 ED 1 B. ADC0 Timing for Internal Trigger Source 2 3 4 5 10 11 12 13 14 Low Power or Convert 1 Track 2 3 4 5 Convert 10 11 Low Power Mode SAR Clocks AD0TM=0 AD Track or Convert Convert Track (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 Page 43 C8051F320/1 5.3.3. Settling Time Requirements Advanced Information Equation 5.1. ADC0 Settling Time Requirements 2 t = ln ------ x R TOTAL C SAMPLE SA n Figure 5.4. ADC0 Equivalent Input Circuits Differential Mode ED IN Where: SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB) t is the required settling time in seconds RTOTAL is the sum of the AMUX0 resistance and any external source resistance. n is the ADC resolution in bits (10). FO VA NC MUX Select Px.x RMUX = 5k RM Single-Ended Mode MUX Select Px.x RMUX = 5k CSAMPLE = 5pF RCInput= RMUX * CSAMPLE CSAMPLE = 5pF RCInput= RMUX * CSAMPLE CSAMPLE = 5pF AD Px.x RMUX = 5k MUX Select Page 44 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. AT Figure 5.4 shows the equivalent ADC0 input circuits for both Differential and Single-ended modes. Notice that the equivalent time constant for both input circuits is the same. The required ADC0 settling time for a given settling accuracy (SA) may be approximated by Equation 5.1. When measuring the Temperature Sensor output or VDD with respect to GND, RTOTAL reduces to RMUX. See Table 5.1 for ADC0 minimum settling time requirements. IO N When the ADC0 input configuration is changed (i.e., a different AMUX0 selection is made), a minimum tracking time is required before an accurate conversion can be performed. This tracking time is determined by the AMUX0 resistance, the ADC0 sampling capacitance, any external source resistance, and the accuracy required for the conversion. Note that in low-power tracking mode, three SAR clocks are used for tracking at the start of every conversion. For most applications, these three SAR clocks will meet the minimum tracking time requirements. Advanced Information C8051F320/1 Figure 5.5. AMX0P: AMUX0 Positive Channel Select Register R R R R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 N Bit0 - - - AMX0P4 AMX0P3 AMX0P2 AMX0P1 AMX0P0 00000000 SFR Address: Only applies to C8051F320; selection RESERVED on C8051F321 devices. (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC AMX0P4-0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 - 11101 11110 11111 ADC0 Positive Input P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 RESERVED Temp Sensor VDD ED IN FO RM AT Page 45 Bits7-5: Bits4-0: UNUSED. Read = 000b; Write = don't care. AMX0P4-0: AMUX0 Positive Input Selection IO 0xBB C8051F320/1 Advanced Information Figure 5.6. AMX0N: AMUX0 Negative Channel Select Register R R R R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Reset Value SFR Address: Bit7 Bit6 Bit5 N Bit0 - - - AMX0N4 AMX0N3 AMX0N2 AMX0N1 AMX0N0 00000000 Only applies to C8051F320; selection RESERVED on C8051F321 devices. AD VA NC AMX0N4-0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 - 11101 11110 11111 ADC0 Negative Input P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 RESERVED VREF GND (ADC in Single-Ended Mode) Page 46 ED IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM AT Bits7-5: Bits4-0: UNUSED. Read = 000b; Write = don't care. AMX0N4-0: AMUX0 Negative Input Selection. Note that when GND is selected as the Negative Input, ADC0 operates in Single-ended mode. For all other Negative Input selections, ADC0 operates in Differential mode. IO 0xBA Advanced Information C8051F320/1 Figure 5.7. ADC0CF: ADC0 Configuration Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value AD0SC4 Bit7 AD0SC3 Bit6 AD0SC2 Bit5 AD0SC1 Bit4 AD0SC0 Bit3 AD0LJST Bit2 Bit1 N Bit0 R/W Bit0 11111000 SFR Address: IO 0xBC Bits7-3: Bit2: R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 IN Figure 5.8. ADC0H: ADC0 Data Word MSB Register R/W Bit3 R/W Bit2 R/W Bit1 Reset Value FO Bits1-0: AD0LJST: ADC0 Left Justify Select. 0: Data in ADC0H:ADC0L registers are right-justified. 1: Data in ADC0H:ADC0L registers are left-justified. UNUSED. Read = 00b; Write = don't care. RM 00000000 SFR Address: SYSCLK AD0SC = --------------------- - 1 CLK SAR ED AT AD0SC4-0: ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from system clock by the following equation, where AD0SC refers to the 5-bit value held in bits AD0SC4-0. SAR Conversion clock requirements are given in Table 5.1. 0xBE Bits7-0: (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ADC0 Data Word High-Order Bits. For AD0LJST = 0: Bits 7-2 are the sign extension of Bit1. Bits 1-0 are the upper 2 bits of the 10-bit ADC0 Data Word. For AD0LJST = 1: Bits 7-0 are the most-significant bits of the 10-bit ADC0 Data Word. Page 47 C8051F320/1 Advanced Information Figure 5.9. ADC0L: ADC0 Data Word LSB Register N Bit0 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Reset Value 00000000 SFR Address: IO 0xBD Bits7-0: AD VA NC Page 48 ED DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. IN FO RM AT ADC0 Data Word Low-Order Bits. For AD0LJST = 0: Bits 7-0 are the lower 8 bits of the 10-bit Data Word. For AD0LJST = 1: Bits 7-6 are the lower 2 bits of the 10-bit Data Word. Bits 5-0 will always read `0'. Advanced Information C8051F320/1 Figure 5.10. ADC0CN: ADC0 Control Register R/W R/W R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W R/W Reset Value AD0EN Bit7 AD0TM Bit6 AD0INT AD0BUSY AD0WINT AD0CM2 AD0CM1 Bit1 N Bit0 AD0CM0 00000000 SFR Address: IO (bit addressable) 0xE8 Bit7: Bit6: Bit5: Bit3: Bits2-0: (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED IN FO Bit4: AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ADC0 Enabled. ADC0 is active and ready for data conversions. AD0TM: ADC0 Track Mode Bit. 0: Normal Track Mode: When ADC0 is enabled, tracking is continuous unless a conversion is in progress. 1: Low-power Track Mode: Tracking Defined by AD0CM2-0 bits (see below). AD0INT: ADC0 Conversion Complete Interrupt Flag. 0: ADC0 has not completed a data conversion since the last time AD0INT was cleared. 1: ADC0 has completed a data conversion. AD0BUSY: ADC0 Busy Bit. Read: 0: ADC0 conversion is complete or a conversion is not currently in progress. AD0INT is set to logic 1 on the falling edge of AD0BUSY. 1: ADC0 conversion is in progress. Write: 0: No Effect. 1: Initiates ADC0 Conversion if AD0CM2-0 = 000b AD0WINT: ADC0 Window Compare Interrupt Flag. 0: ADC0 Window Comparison Data match has not occurred since this flag was last cleared. 1: ADC0 Window Comparison Data match has occurred. AD0CM2-0: ADC0 Start of Conversion Mode Select. When AD0TM = 0: 000: ADC0 conversion initiated on every write of `1' to AD0BUSY. 001: ADC0 conversion initiated on overflow of Timer 0. 010: ADC0 conversion initiated on overflow of Timer 2. 011: ADC0 conversion initiated on overflow of Timer 1. 100: ADC0 conversion initiated on rising edge of external CNVSTR. 101: ADC0 conversion initiated on overflow of Timer 3. 11x: Reserved. When AD0TM = 1: 000: Tracking initiated on write of `1' to AD0BUSY and lasts 3 SAR clocks, followed by conversion. 001: Tracking initiated on overflow of Timer 0 and lasts 3 SAR clocks, followed by conversion. 010: Tracking initiated on overflow of Timer 2 and lasts 3 SAR clocks, followed by conversion. 011: Tracking initiated on overflow of Timer 1 and lasts 3 SAR clocks, followed by conversion. 100: ADC0 tracks only when CNVSTR input is logic low; conversion starts on rising CNVSTR edge. 101: Tracking initiated on overflow of Timer 3 and lasts 3 SAR clocks, followed by conversion. 11x: Reserved. RM AT Page 49 C8051F320/1 5.4. Advanced Information Programmable Window Detector Figure 5.11. ADC0GTH: ADC0 Greater-Than Data High Byte Register R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 RM R/W Bit2 AT R/W Bit1 R/W Bit1 The Window Detector registers must be written with the same format (left/right justified, signed/unsigned) as that of the current ADC configuration (left/right justified, single-ended/differential). IO The ADC Programmable Window Detector continuously compares the ADC0 conversion results to user-programmed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system response times. The window detector interrupt flag (AD0WINT in register ADC0CN) can also be used in polled mode. The ADC0 Greater-Than (ADC0GTH, ADC0GTL) and Less-Than (ADC0LTH, ADC0LTL) registers hold the comparison values. The window detector flag can be programmed to indicate when measured data is inside or outside of the user-programmed limits, depending on the contents of the ADC0 Less-Than and ADC0 Greater-Than registers. N R/W Bit0 R/W Bit0 Reset Value 11111111 SFR Address: 0xC4 Bits7-0: High byte of ADC0 Greater-Than Data Word. Figure 5.12. ADC0GTL: ADC0 Greater-Than Data Low Byte Register R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 Reset Value IN FO ED 11111111 SFR Address: 0xC3 AD Page 50 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. VA NC Bits7-0: Low byte of ADC0 Greater-Than Data Word. Advanced Information C8051F320/1 Figure 5.13. ADC0LTH: ADC0 Less-Than Data High Byte Register N Bit0 R/W Bit0 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Reset Value 00000000 SFR Address: IO 0xC6 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 RM R/W Bit2 Figure 5.14. ADC0LTL: ADC0 Less-Than Data Low Byte Register R/W Bit1 Reset Value AT Bits7-0: High byte of ADC0 Less-Than Data Word. 00000000 SFR Address: Bits7-0: Low byte of ADC0 Less-Than Data Word. (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED IN FO 0xC5 Page 51 C8051F320/1 5.4.1. Advanced Information Window Detector In Single-Ended Mode Figure 5.15. ADC Window Compare Example: Right-Justified Single-Ended Data ADC0H:ADC0L Input Voltage (Px.x - GND) VREF x (1023/1024) 0x03FF AD0WINT not affected 0x0081 VREF x (128/1024) 0x0080 0x007F 0x0041 VREF x (64/1024) 0x0040 0x003F ADC0GTH:ADC0GTL ADC0LTH:ADC0LTL Input Voltage (Px.x - GND) ADC0H:ADC0L VREF x (1023/1024) RM 0 AT 0x03FF 0x0081 0x0080 0x007F 0x0041 0x0040 0x003F 0x0000 Figure 5.15 shows two example window comparisons for right-justified, single-ended data, with ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). In single-ended mode, the input voltage can range from `0' to VREF * (1023/1024) with respect to GND, and is represented by a 10-bit unsigned integer value. In the left example, an AD0WINT interrupt will be generated if the ADC0 conversion word (ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and ADC0LTH:ADC0LTL (if 0x0040 < ADC0H:ADC0L < 0x0080). In the right example, and AD0WINT interrupt will be generated if the ADC0 conversion word is outside of the range defined by the ADC0GT and ADC0LT registers (if ADC0H:ADC0L < 0x0040 or ADC0H:ADC0L > 0x0080). Figure 5.16 shows an example using left-justified data with equivalent ADC0GT and ADC0LT register settings.. IO N AD0WINT=1 FO VREF x (128/1024) ADC0GTH:ADC0GTL AD0WINT not affected ADC0LTH:ADC0LTL AD0WINT=1 IN VREF x (64/1024) AD0WINT not affected 0 0x0000 AD0WINT=1 Figure 5.16. ADC Window Compare Example: Left-Justified Single-Ended Data VA NC ADC0H:ADC0L ED AD0WINT not affected ADC0H:ADC0L Input Voltage (Px.x - GND) VREF x (1023/1024) 0xFFC0 Input Voltage (Px.x - GND) VREF x (1023/1024) 0xFFC0 AD0WINT=1 0x2040 0x2040 VREF x (128/1024) 0x2000 0x1FC0 0x1040 ADC0GTH:ADC0GTL AD0WINT not affected ADC0LTH:ADC0LTL VREF x (128/1024) 0x2000 0x1FC0 0x1040 ADC0LTH:ADC0LTL AD0WINT=1 VREF x (64/1024) AD 0x1000 ADC0GTH:ADC0GTL VREF x (64/1024) 0x1000 0x0FC0 0x0FC0 AD0WINT not affected 0 0x0000 AD0WINT=1 0 0x0000 Page 52 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. Advanced Information 5.4.2. Window Detector In Differential Mode C8051F320/1 Figure 5.17. ADC Window Compare Example: Right-Justified Differential Data ADC0H:ADC0L Input Voltage (Px.x - Px.x) VREF x (511/512) 0x01FF AD0WINT not affected 0x0041 VREF x (64/512) 0x0040 0x003F 0x0000 0xFFFF 0xFFFE ADC0LTH:ADC0LTL Input Voltage (Px.x - Px.x) ADC0H:ADC0L VREF x (511/512) RM -VREF -VREF AT 0x01FF 0x0041 0x0040 0x003F 0x0000 0xFFFF 0xFFFE 0x0200 ADC0H:ADC0L 0x7FC0 0x1040 0x1000 0x0FC0 0x0000 0xFFC0 0xFF80 0x8000 Figure 5.17 shows two example window comparisons for right-justified, differential data, with ADC0LTH:ADC0LTL = 0x0040 (+64d) and ADC0GTH:ADC0GTH = 0xFFFF (-1d). In differential mode, the measurable voltage between the input pins is between -VREF and VREF*(511/512). Output codes are represented as 10bit 2's complement signed integers. In the left example, an AD0WINT interrupt will be generated if the ADC0 conversion word (ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and ADC0LTH:ADC0LTL (if 0xFFFF (-1d) < ADC0H:ADC0L < 0x0040 (64d)). In the right example, an AD0WINT interrupt will be generated if the ADC0 conversion word is outside of the range defined by the ADC0GT and ADC0LT registers (if ADC0H:ADC0L < 0xFFFF (-1d) or ADC0H:ADC0L > 0x0040 (+64d)). Figure 5.18 shows an example using left-justified data with equivalent ADC0GT and ADC0LT register settings.. IO N AD0WINT=1 FO VREF x (64/512) ADC0GTH:ADC0GTL AD0WINT not affected ADC0LTH:ADC0LTL AD0WINT=1 VREF x (-1/512) ADC0GTH:ADC0GTL IN VREF x (-1/512) AD0WINT not affected -VREF 0x0200 AD0WINT=1 Figure 5.18. ADC Window Compare Example: Left-Justified Differential Data Input Voltage (Px.x - Px.x) VREF x (511/512) VA NC ADC0H:ADC0L 0x7FC0 ED AD0WINT not affected Input Voltage (Px.x - Px.y) VREF x (511/512) AD0WINT=1 0x1040 VREF x (64/512) 0x1000 0x0FC0 ADC0LTH:ADC0LTL AD0WINT=1 VREF x (64/512) ADC0GTH:ADC0GTL AD0WINT not affected ADC0LTH:ADC0LTL VREF x (-1/512) AD 0x0000 0xFFC0 0xFF80 ADC0GTH:ADC0GTL VREF x (-1/512) AD0WINT not affected AD0WINT=1 -VREF 0x8000 (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 Page 53 C8051F320/1 Advanced Information Table 5.1. ADC0 Electrical Characteristics VDD = 3.0 V, VREF = 2.40 V, -40C to +85C unless otherwise specified PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full Scale Error Offset Temperature Coefficient Signal-to-Noise Plus Distortion Total Harmonic Distortion Spurious-Free Dynamic Range CONVERSION RATE SAR Conversion Clock Conversion Time in SAR Clocks Track/Hold Acquisition Time Throughput Rate ANALOG INPUTS Input Voltage Range Input Capacitance TEMPERATURE SENSOR Linearity Gain Offset Up to the 5 harmonic th CONDITIONS MIN TYP 10 0.5 0.5 1 -5 MAX UNITS bits LSB LSB LSB LSB ppm/C dB dB dB Guaranteed Monotonic Differential mode DYNAMIC PERFORMANCE (10 kHz sine-wave Single-ended input, 0 to 1 dB below Full Scale, 200 ksps) RM FO AT 53 10 300 0 IO 3.6 55.5 -67 78 5 TBD 2.86 0.776 400 0.3 N TBD TBD TBD 200 VDD 900 MHz clocks ns ksps V pF C mV / C mV POWER SPECIFICATIONS Power Supply Current (VDD supplied to ADC0) Power Supply Rejection VA NC ED Temp = 0 C Operating Mode, 200 ksps IN A mV/V AD Page 54 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. Advanced Information 6. VOLTAGE REFERENCE C8051F320/1 ED REFSL TEMPE BIASE REFBE IN REF0CN 0 1 TEMPE Figure 6.1. Voltage Reference Functional Block Diagram FO AD0EN IOSCEN CLKMUL Enable REFBE EN The temperature sensor connects to the ADC0 positive input multiplexer (see Section "5.1. Analog Multiplexer" on page 40 for details). The TEMPE bit in register REF0CN enables/disables the temperature sensor. While disabled, the temperature sensor defaults to a high impedance state and any ADC0 measurements performed on the sensor result in meaningless data. RM EN EN EN Important Note About the VREF Input: Port pin P0.7 is used as the external VREF input. When using an external voltage reference, P0.7 should be configured as analog input and skipped by the Digital Crossbar. To configure P0.7 as analog input, set to `1' Bit7 in register P0MDIN. To configure the Crossbar to skip P0.7, set to `1' Bit7 in register P0SKIP. Refer to Section "14. Port Input/Output" on page 125 for complete Port I/O configuration details. AT ADC Bias Temp Sensor Reference Bias The BIASE bit enables the internal ADC bias generator, which is used by the ADC and Internal Oscillator. This enable is forced to logic 1 when either of the aforementioned peripherals is enabled. The ADC bias generator may be enabled manually by writing a `1' to the BIASE bit in register REF0CN; see Figure 6.2 for REF0CN register details. The Reference bias generator (see Figure 6.1) is used by the Internal Voltage Reference, Temperature Sensor, and Clock Multiplier. The Reference bias is automatically enabled when any of the aforementioned peripherals are enabled. The electrical specifications for the voltage reference and bias circuits are given in Table 6.1. VDD VA NC R1 External Voltage Reference Circuit VREF GND VDD AD Internal Reference (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 IO N The Voltage reference MUX on C8051F320/1 devices is configurable to use an externally connected voltage reference, the internal reference voltage generator, or the power supply voltage VDD (see Figure 6.1). The REFSL bit in the Reference Control register (REF0CN) selects the reference source. For the internal reference or an external source, REFSL should be set to `0'; For VDD as the reference source, REFSL should be set to `1'. To ADC, Internal Oscillator To Analog Mux VREF (to ADC) To Clock Multiplier, Temp Sensor Page 55 C8051F320/1 Advanced Information Figure 6.2. REF0CN: Reference Control Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 N Bit0 - - - - REFSL TEMPE BIASE REFBE 00000000 SFR Address: Bit2: Bit1: Table 6.1. Voltage Reference Electrical Characteristics VDD = 3.0 V; -40C TO +85C UNLESS OTHERWISE SPECIFIED PARAMETER Output Voltage CONDITIONS MIN 2.36 TYP 2.43 15 1.5 2 20 10 0 Sample Rate = 200 ksps; VREF = 3.0 V BIASE = `1' 12 TBD TBD VDD MAX 2.48 10 UNITS V mA ppm/C ppm/A ms s s V A A A INTERNAL REFERENCE (REFBE = 1) VREF Short-Circuit Current Load Regulation VREF Temperature Coefficient VREF Turn-on Time 1 VREF Turn-on Time 2 VREF Turn-on Time 3 Input Voltage Range Input Current EXTERNAL REFERENCE (REFBE = 0) BIAS GENERATORS ADC Bias Generator Reference Bias Generator AD VA NC 25C ambient Load = 0 to 200 A to GND 4.7F tantalum, 0.1F ceramic bypass 0.1F ceramic bypass no bypass cap Page 56 ED IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO Bit0: RM AT Bits7-3: Bit3: UNUSED. Read = 00000b; Write = don't care. REFSL: Voltage Reference Select. This bit selects the source for the internal voltage reference. 0: VREF pin used as voltage reference. 1: VDD used as voltage reference. TEMPE: Temperature Sensor Enable Bit. 0: Internal Temperature Sensor off. 1: Internal Temperature Sensor on. BIASE: Internal Analog Bias Generator Enable Bit. 0: Internal Bias Generator off. 1: Internal Bias Generator on. REFBE: Internal Reference Buffer Enable Bit. 0: Internal Reference Buffer disabled. 1: Internal Reference Buffer enabled. Internal voltage reference driven on the VREF pin. IO 0xD1 Advanced Information 7. COMPARATORS C8051F320/1 Figure 7.1. Comparator0 Functional Block Diagram CP0EN CP0OUT CP0RIF CP0FIF CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 CPT0CN IN FO VDD Important Note About Comparator Inputs: The Port pins selected as Comparator inputs should be configured as analog inputs in their associated Port configuration register, and configured to be skipped by the Crossbar (for details on Port configuration, see Section "14.3. General Purpose Port I/O" on page 132). RM D SET The Comparator0 inputs are selected in the CPT0MX register (Figure 7.5). The CMX0P1-CMX0P0 bits select the Comparator0 positive input; the CMX0N1-CMX0N0 bits select the Comparator0 negative input. The Comparator1 inputs are selected in the CPT1MX register (Figure 7.8). The CMX1P1-CMX1P0 bits select the Comparator1 positive input; the CMX1N1-CMX1N0 bits select the Comparator1 negative input. AT D SET Each Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the Port pins: a synchronous "latched" output (CP0, CP1), or an asynchronous "raw" output (CP0A, CP1A). The asynchronous signal is available even when the system clock is not active. This allows the Comparators to operate and generate an output with the device in STOP mode. When assigned to a Port pin, the Comparator outputs may be configured as open drain or push-pull (see Section "14.2. Port I/O Initialization" on page 129). Comparator0 may also be used as a reset source (see Section "10.5. Comparator0 Reset" on page 100). IO CPT0MX VA NC CMX0P1 CMX0P0 ED CMX0N1 CMX0N0 P1.0 P1.4 P2.0 P2.4 CP0 Rising-edge CP0 + N Interrupt Logic Crossbar C8051F320/1 devices include two on-chip programmable voltage Comparators: Comparator0 is shown in Figure 7.1; Comparator1 is shown in Figure 7.2. The two Comparators operate identically with the following exceptions: (1) Their input selections differ as shown in Figure 7.1 and Figure 7.2; (2) Comparator0 can be used as a reset source. CP0 Interrupt CP0 Falling-edge CP0RIE CP0FIE + Q Q CP0 GND Reset Decision Tree CP0RIE CP0FIE CLR Q CLR Q P1.1 P1.5 P2.1 P2.5 (SYNCHRONIZER) AD CP0 - CP0A Note: P2.4 and P2.5 available only on C8051F320 CPT0MD CP0MD1 CP0MD0 (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 Page 57 C8051F320/1 Advanced Information Figure 7.2. Comparator1 Functional Block Diagram CP1OUT CP1RIF CP1FIF CP1HYP1 CP1HYP0 CP1HYN1 CP1HYN0 CPT1CN VDD RM CP1 Rising-edge Interrupt Logic D SET CP1EN AT D SET Comparator response time may be configured in software via the CPTnMD registers (see Figure 7.6 and Figure 7.9). Selecting a longer response time reduces the Comparator supply current. See Table 7.1 for complete timing and supply current specifications. IO Comparator outputs can be polled in software, used as an interrupt source, and/or routed to a Port pin. When routed to a Port pin, Comparator outputs are available asynchronous or synchronous to the system clock; the asynchronous output is available even in STOP mode (with no system clock active). When disabled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state, and supply current falls to less than 100 nA. See Section "14.1. Priority Crossbar Decoder" on page 127 for details on configuring Comparator outputs via the digital Crossbar. Comparator inputs can be externally driven from -0.25 V to (VDD) + 0.25 V without damage or upset. The complete Comparator electrical specifications are given in Table 7.1. N Crossbar CPT1MX CMX1P1 CMX1P0 FO CMX1N1 CMX1N0 CP1 Interrupt P1.6 P2.2 P2.6 CP1 + IN P1.2 CP1 Falling-edge CP1RIE CP1FIE CP1 ED + Q Q GND CLR Q CLR Q P1.3 P1.7 P2.3 P2.7 (SYNCHRONIZER) VA NC CP1 - CP1A Note: P2.6 and P2.7 available only on C8051F320 CPT1MD CP1RIE CP1FIE CP1MD1 CP1MD0 AD Page 58 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. Advanced Information C8051F320/1 Figure 7.3. Comparator Hysteresis Plot VIN- CP0- OUT CIRCUIT CONFIGURATION Positive Hysteresis Voltage (Programmed with CP0HYP Bits) VIN- INPUTS VIN+ RM VOH OUTPUT VOL IN Maximum Positive Hysteresis FO Negative Hysteresis Disabled Maximum Negative Hysteresis Positive Hysteresis Disabled Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Interrupt enable and priority control, see Section "8.3. Interrupt Handler" on page 58.) The CPnFIF flag is set to `1' upon a Comparator falling-edge, and the CPnRIF flag is set to `1' upon the Comparator rising-edge. Once set, these bits remain set until cleared by software. The output state of the Comparator can be obtained at any time by reading the CPnOUT bit. The Comparator is enabled by setting the CPnEN bit to `1', and is disabled by clearing this bit to `0'. (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC Comparator hysteresis is programmed using Bits3-0 in the Comparator Control Register CPTnCN (shown in Figure 7.4 and Figure 7.7). The amount of negative hysteresis voltage is determined by the settings of the CPnHYN bits. As shown in Figure 7.3, settings of 20, 10 or 5 mV of negative hysteresis can be programmed, or negative hysteresis can be disabled. In a similar way, the amount of positive hysteresis is determined by the setting the CPnHYP bits. ED AT Negative Hysteresis Voltage (Programmed by CP0HYN Bits) IO Page 59 VIN+ CP0+ + CP0 _ N C8051F320/1 Advanced Information Figure 7.4. CPT0CN: Comparator0 Control Register CP0EN Bit7 CP0OUT Bit6 CP0RIF Bit5 CP0FIF Bit4 CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 00000000 IO Bit3 Bit2 Bit1 N Bit0 R/W R R/W R/W R/W R/W R/W R/W Reset Value SFR Address: 0x9B Bit7: Bit6: Bit5: Bit4: Bits3-2: Bits1-0: AD VA NC Page 60 ED CP0EN: Comparator0 Enable Bit. 0: Comparator0 Disabled. 1: Comparator0 Enabled. CP0OUT: Comparator0 Output State Flag. 0: Voltage on CP0+ < CP0-. 1: Voltage on CP0+ > CP0-. CP0RIF: Comparator0 Rising-Edge Flag. 0: No Comparator0 Rising Edge has occurred since this flag was last cleared. 1: Comparator0 Rising Edge has occurred. CP0FIF: Comparator0 Falling-Edge Flag. 0: No Comparator0 Falling-Edge has occurred since this flag was last cleared. 1: Comparator0 Falling-Edge Interrupt has occurred. CP0HYP1-0: Comparator0 Positive Hysteresis Control Bits. 00: Positive Hysteresis Disabled. 01: Positive Hysteresis = 5 mV. 10: Positive Hysteresis = 10 mV. 11: Positive Hysteresis = 20 mV. CP0HYN1-0: Comparator0 Negative Hysteresis Control Bits. 00: Negative Hysteresis Disabled. 01: Negative Hysteresis = 5 mV. 10: Negative Hysteresis = 10 mV. 11: Negative Hysteresis = 20 mV. IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM AT Advanced Information C8051F320/1 Figure 7.5. CPT0MX: Comparator0 MUX Selection Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 CMX0N1 Bit5 CMX0N0 Bit4 Bit3 Bit2 CMX0P1 Bit1 N Bit0 CMX0P0 00000000 SFR Address: IO 0x9F P2.5 P2.4 and P2.5 available only on C8051F320 devices; selection reserved on C8051F321 devices. Note: (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED CMX0P1 CMX0P0 0 0 0 1 1 0 1 1 Positive Input P1.0 P1.4 P2.0 P2.4 IN FO Bits3-2: Bits1-0: UNUSED. Read = 00b, Write = don't care. CMX0P1-CMX0P0: Comparator0 Positive Input MUX Select. These bits select which Port pin is used as the Comparator0 positive input. RM CMX0N1 CMX0N0 0 0 0 1 1 0 1 1 Negative Input P1.1 P1.5 P2.1 AT Bits7-6: Bits5-4: UNUSED. Read = 00b, Write = don't care. CMX0N1-CMX0N0: Comparator0 Negative Input MUX Select. These bits select which Port pin is used as the Comparator0 negative input. Page 61 C8051F320/1 Advanced Information Figure 7.6. CPT0MD: Comparator0 Mode Selection Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 CP0RIE Bit5 CP0FIE Bit4 Bit3 Bit2 CP0MD1 Bit1 N Bit0 CP0MD0 00000010 SFR Address: IO AT 0x9D Bits7-6: Bit5: Bit4: Bits3-2: Bits1-0: AD VA NC Page 62 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. ED IN Mode 0 1 2 3 CP0MD1 0 0 1 1 CP0MD0 CP0 Response Time (TYP) 0 100 ns 1 175 ns 0 320 ns 1 1050 ns FO RM UNUSED. Read = 00b. Write = don't care. CP0RIE: Comparator0 Rising-Edge Interrupt Enable. 0: Comparator0 rising-edge interrupt disabled. 1: Comparator0 rising-edge interrupt enabled. CP0FIE: Comparator0 Falling-Edge Interrupt Enable. 0: Comparator0 falling-edge interrupt disabled. 1: Comparator0 falling-edge interrupt enabled. UNUSED. Read = 00b. Write = don't care. CP0MD1-CP0MD0: Comparator0 Mode Select These bits select the response time for Comparator0. Advanced Information C8051F320/1 Figure 7.7. CPT1CN: Comparator1 Control Register R/W R R/W R/W R/W Bit3 R/W Bit2 R/W Bit1 R/W Reset Value SFR Address: Bit7 Bit6 Bit5 Bit4 N Bit0 CP1EN CP1OUT CP1RIF CP1FIF CP1HYP1 CP1HYP0 CP1HYN1 CP1HYN0 00000000 Bit7: Bit6: Bit5: Bit4: Bits3-2: Bits1-0: (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED CP1EN: Comparator1 Enable Bit. 0: Comparator1 Disabled. 1: Comparator1 Enabled. CP1OUT: Comparator1 Output State Flag. 0: Voltage on CP1+ < CP1-. 1: Voltage on CP1+ > CP1-. CP1RIF: Comparator1 Rising-Edge Flag. 0: No Comparator1 Rising Edge has occurred since this flag was last cleared. 1: Comparator1 Rising Edge has occurred. CP1FIF: Comparator1 Falling-Edge Flag. 0: No Comparator1 Falling-Edge has occurred since this flag was last cleared. 1: Comparator1 Falling-Edge has occurred. CP1HYP1-0: Comparator1 Positive Hysteresis Control Bits. 00: Positive Hysteresis Disabled. 01: Positive Hysteresis = 5 mV. 10: Positive Hysteresis = 10 mV. 11: Positive Hysteresis = 20 mV. CP1HYN1-0: Comparator1 Negative Hysteresis Control Bits. 00: Negative Hysteresis Disabled. 01: Negative Hysteresis = 5 mV. 10: Negative Hysteresis = 10 mV. 11: Negative Hysteresis = 20 mV. IN FO RM AT IO 0x9A Page 63 C8051F320/1 Advanced Information Figure 7.8. CPT1MX: Comparator1 MUX Selection Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 CMX1N1 Bit5 CMX1N0 Bit4 Bit3 Bit2 CMX1P1 Bit1 N Bit0 CMX1P0 00000000 SFR Address: IO 0x9E P2.7 Note: P2.6 and P2.7 available only on C8051F320 devices; selection reserved on C8051F321 devices. AD VA NC Page 64 ED CMX1P1 CMX1P0 0 0 0 1 1 0 1 1 Positive Input P1.2 P1.6 P2.2 P2.6 IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO Bits3-2: Bits1-0: UNUSED. Read = 00b, Write = don't care. CMX1P1-CMX1P0: Comparator1 Positive Input MUX Select. These bits select which Port pin is used as the Comparator1 positive input. RM CMX1N1 CMX1N0 0 0 0 1 1 0 1 1 Negative Input P1.3 P1.7 P2.3 AT Bits7-6: Bits5-4: UNUSED. Read = 00b, Write = don't care. CMX1N1-CMX1N0: Comparator1 Negative Input MUX Select. These bits select which Port pin is used as the Comparator1 negative input. Advanced Information C8051F320/1 Figure 7.9. CPT1MD: Comparator1 Mode Selection Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 CP1RIE Bit5 CP1FIE Bit4 Bit3 Bit2 CP1MD1 Bit1 N Bit0 CP1MD0 00000010 SFR Address: IO AT 0x9C Bits7-6: Bit5: Bit4: Bits1-0: (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED IN Mode 0 1 2 3 CP1MD1 0 0 1 1 CP1MD0 CP1 Response Time (TYP) 0 100 ns 1 175 ns 0 320 ns 1 1050 ns FO RM UNUSED. Read = 00b, Write = don't care. CP1RIE: Comparator1 Rising-Edge Interrupt Enable. 0: Comparator1 rising-edge interrupt disabled. 1: Comparator1 rising-edge interrupt enabled. CP1FIE: Comparator1 Falling-Edge Interrupt Enable. 0: Comparator1 falling-edge interrupt disabled. 1: Comparator1 falling-edge interrupt enabled. CP1MD1-CP1MD0: Comparator1 Mode Select. These bits select the response time for Comparator1. Page 65 C8051F320/1 Advanced Information Table 7.1. Comparator Electrical Characteristics VDD = 3.0 V, -40C to +85C unless otherwise noted. All specifications apply to both Comparator0 and Comparator1 unless otherwise noted. Response Time: Mode 0, Vcm = 1.5 V Response Time: Mode 1, Vcm = 1.5 V Response Time: Mode 2, Vcm = 1.5 V Response Time: Mode 3, Vcm = 1.5 V Common-Mode Rejection Ratio Positive Hysteresis 1 Positive Hysteresis 2 Positive Hysteresis 3 Positive Hysteresis 4 Negative Hysteresis 1 Negative Hysteresis 2 Negative Hysteresis 3 Negative Hysteresis 4 Inverting or Non-Inverting Input Voltage Range Input Capacitance Input Bias Current Input Offset Voltage POWER SUPPLY Power-up Time CP0HYP1-0 = 00 CP0HYP1-0 = 01 CP0HYP1-0 = 10 CP0HYP1-0 = 11 CP0HYN1-0 = 00 CP0HYN1-0 = 01 CP0HYN1-0 = 10 CP0HYN1-0 = 11 CP0+ - CP0- = 100 mV CP0+ - CP0- = -100 mV CP0+ - CP0- = 100 mV CP0+ - CP0- = -100 mV CP0+ - CP0- = 100 mV CP0+ - CP0- = -100 mV CP0+ - CP0- = 100 mV CP0+ - CP0- = -100 mV 100 250 175 500 320 N 4 1 7 1 7 1 PARAMETER CONDITIONS MIN TYP MAX UNITS ns ns ns ns ns ns ns ns mV/V mV mV mV mV mV mV mV mV V pF nA RM AT 3 7 15 3 7 15 -0.25 -5 FO IO 1100 1050 5200 1.5 0 5 10 20 0 5 10 20 15 25 15 25 VDD + 0.25 7 0.001 +5 0.1 10 7.6 3.2 1.3 0.4 VA NC ED IN mV mV/V s A A A A Power Supply Rejection Mode 0 Mode 1 Mode 2 Mode 3 Supply Current at DC Vcm is the common-mode voltage on CP0+ and CP0-. AD Page 66 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. Advanced Information 8. VOLTAGE REGULATOR (REG0) C8051F320/1 8.2. VBUS Detection Important Note: When USB is selected as a reset source, a system reset will be generated when the VBUS signal matches the polarity selected by the VBPOL bit. See Section "10. Reset Sources" on page 97 for details on selecting USB as a reset source. Table 8.1. Voltage Regulator Electrical Specifications VDD = 3.0 V; -40C to +85C unless otherwise specified Input Voltage Range Output Voltage PARAMETER CONDITIONS MIN 4.0 3.0 1.0 3.3 1.8 70 30 TYP MAX UNITS 5.25 3.6 4.0 TBD TBD V V V A VBUS Detection Input Threshold Bias Current (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED Output Current = 0 to 100 mA Normal Mode (REGMOD = `0') Low Power Mode (REGMOD = `1') IN When the USB Function Controller is used (see section Section "15. Universal Serial Bus Controller (USB0)" on page 141), the VBUS signal should be connected to the VBUS pin. The VBSTAT bit (register REG0CN) indicates the current logic level of the VBUS signal. If enabled, a VBUS interrupt will be generated when the VBUS signal matches the polarity selected by the VBPOL bit in register REG0CN. The VBUS interrupt is level-sensitive, and has no associated interrupt pending flag. The VBUS interrupt will be active as long as the VBUS signal matches the polarity selected by VBPOL. See Table 8.1 for VBUS input parameters. FO RM REG0 offers a low power mode intended for use when the device is in suspend mode. In this low power mode, the REG0 output remains as specified; however the REG0 dynamic performance (response time) is degraded. See Table 8.1 for normal and low power mode supply current specifications. The REG0 mode selection is controlled via the REGMOD bit in register REG0CN. AT 8.1. Regulator Mode Selection IO Note that the VBUS signal must be connected to the VBUS pin when using the device in a USB network. The VBUS signal should only be connected to the REGIN pin when operating the device as a bus-powered function. REG0 configuration options are shown in Figure 8.1 - Figure 8.4. N C8051F320/1 devices include a 5 V-to-3 V voltage regulator (REG0). When enabled, the REG0 output appears on the VDD pin and can be used to power external devices. REG0 can be enabled/disabled by software using bit REGEN in register REG0CN. See Table 8.1 for REG0 electrical characteristics. Page 67 C8051F320/1 Advanced Information Figure 8.1. REG0 Configuration: USB Bus-Powered C8051F320/1 From VBUS REGIN 5V In VBUS Sense Voltage Regulator (REG0) To 3V Power Net RM AT 3V Out 3V Out IO Device Power Net Device Power Net VBUS VDD C8051F320/1 From VBUS VBUS IN 5V In FO Figure 8.2. REG0 Configuration: USB Self-Powered VBUS Sense From 5V Power Net ED REGIN Voltage Regulator (REG0) To 3V Power Net AD VA NC VDD Page 68 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. N Advanced Information C8051F320/1 Figure 8.3. REG0 Configuration: USB Self-Powered, Regulator Disabled C8051F320/1 VBUS Sense REGIN 5V In Voltage Regulator (REG0) RM AT 3V Out 3V Out IO Device Power Net Device Power Net From VBUS VBUS From 3V Power Net VDD C8051F320/1 VBUS IN 5V In FO Figure 8.4. REG0 Configuration: No USB Connection VBUS Sense From 5V Power Net ED REGIN Voltage Regulator (REG0) To 3V Power Net (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC VDD N Page 69 C8051F320/1 Advanced Information Figure 8.5. REG0CN: Voltage Regulator Control R/W R R/W R/W Bit4 R/W Bit3 R/W R/W N R/W Bit0 Reset Value REGDIS Bit7 VBSTAT Bit6 VBPOL Bit5 REGMOD Reserved Reserved Bit2 Reserved Bit1 Reserved 00000000 SFR Address: IO 0xC9 Bit6: Bit5: Bit4: Bits3-0: AD VA NC Page 70 ED DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. IN FO RM AT Bit7: REGDIS: Voltage Regulator Disable. 0: Voltage Regulator Enabled. 1: Voltage Regulator Disabled. VBSTAT: VBUS Signal Status. 0: VBUS signal currently absent (device not attached to USB network). 1: VBUS signal currently preset (device attached to USB network). VBPOL: VBUS Interrupt Polarity Select. This bit selects the VBUS interrupt polarity. 0: VBUS interrupt active when VBUS is low. 1: VBUS interrupt active when VBUS is high. REGMOD: Voltage Regulator Mode Select. This bit selects the Voltage Regulator mode. When REGMOD is set to `1', the voltage regulator operates in low power (suspend) mode. 0: USB0 Voltage Regulator in normal mode. 1: USB0 Voltage Regulator in low power mode. Reserved. Read = 0000b. Must Write = 0000b. Advanced Information 9. CIP-51 MICROCONTROLLER C8051F320/1 The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as additional custom peripherals and functions to extend its capability (see Figure 9.1 for a block diagram). The CIP-51 includes the following features: Figure 9.1. CIP-51 Block Diagram IN D8 D8 D8 FO DATA BUS TMP2 D8 RM B REGISTER SRAM ADDRESS REGISTER D8 D8 - Fully Compatible with MCS-51 Instruction Set 25 MIPS Peak Throughput with 25 MHz Clock 0 to 25 MHz Clock Frequency 256 Bytes of Internal RAM 25 Port I/O - Extended Interrupt Handler Reset Input Power Management Modes On-chip Debug Logic Program and Data Memory Security ACCUMULATOR STACK POINTER DATA BUS ED TMP1 PSW D8 ALU D8 SRAM (256 X 8) D8 VA NC DATA BUS SFR_ADDRESS D8 BUFFER DATA POINTER D8 SFR BUS INTERFACE SFR_CONTROL SFR_WRITE_DATA SFR_READ_DATA PC INCREMENTER AD DATA BUS PROGRAM COUNTER (PC) D8 MEM_ADDRESS MEM_CONTROL PRGM. ADDRESS REG. A16 MEMORY INTERFACE MEM_WRITE_DATA MEM_READ_DATA PIPELINE RESET CLOCK STOP IDLE POWER CONTROL REGISTER D8 D8 CONTROL LOGIC INTERRUPT INTERFACE SYSTEM_IRQs EMULATION_IRQ D8 (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 D8 AT IO The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51TM instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has a superset of all the peripherals included with a standard 8051. Included are four 16-bit counter/timers (see description in Section 19), an enhanced full-duplex UART (see description in Section 17), an Enhanced SPI (see description in Section 18), 256 bytes of internal RAM, 128 byte Special Function Register (SFR) address space (Section 9.2.6), and 25 Port I/O (see description in Section 14). The CIP-51 also includes on-chip debug hardware (see description in Section 21), and interfaces directly with the analog and digital subsystems providing a complete data acquisition or control-system solution in a single integrated circuit. N Page 71 C8051F320/1 Advanced Information Clocks to Execute Number of Instructions 1 26 2 50 2/3 5 3 14 3/4 7 IO 4 3 4/5 1 With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that for execution time. 5 2 8 1 AD VA NC Page 72 ED The CIP-51 is supported by development tools from Cygnal Integrated Products and third party vendors. Cygnal provides an integrated development environment (IDE) including editor, macro assembler, debugger and programmer. The IDE's debugger and programmer interface to the CIP-51 via the C2 interface to provide fast and efficient in-system device programming and debugging. Third party macro assemblers and C compilers are also available. IN The on-chip debug support logic facilitates full speed in-circuit debugging, allowing the setting of hardware breakpoints, starting, stopping and single stepping through program execution (including interrupt service routines), examination of the program's call stack, and reading/writing the contents of registers and memory. This method of on-chip debugging is completely non-intrusive, requiring no RAM, Stack, timers, or other on-chip resources. C2 details can be found in Section "21. C2 Interface" on page 249. DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM Programming and Debugging Support In-system programming of the FLASH program memory and communication with on-chip debug support logic is accomplished via the Cygnal 2-Wire Development Interface (C2). Note that the re-programmable FLASH can also be read and changed a single byte at a time by the application software using the MOVC and MOVX instructions. This feature allows program memory to be used for non-volatile data storage as well as updating program code under software control. AT N Performance The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more than eight system clock cycles. Advanced Information 9.1. Instruction Set C8051F320/1 9.1.1. Instruction and CPU Timing 9.1.2. MOVX Instruction and Program Memory Table 9.1. CIP-51 Instruction Set Summary Mnemonic ADD A, Rn ADD A, direct ADD A, @Ri ADD A, #data ADDC A, Rn ADDC A, direct ADDC A, @Ri ADDC A, #data SUBB A, Rn SUBB A, direct SUBB A, @Ri SUBB A, #data INC A INC Rn INC direct INC @Ri DEC A DEC Rn DEC direct DEC @Ri INC DPTR Description Bytes 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 1 2 1 1 Clock Cycles 1 2 2 2 1 2 2 2 1 2 2 2 1 1 2 2 1 1 2 2 1 ARITHMETIC OPERATIONS Add register to A Add direct byte to A Add indirect RAM to A Add immediate to A Add register to A with carry Add direct byte to A with carry Add indirect RAM to A with carry Add immediate to A with carry Subtract register from A with borrow Subtract direct byte from A with borrow Subtract indirect RAM from A with borrow Subtract immediate from A with borrow Increment A Increment register Increment direct byte Increment indirect RAM Decrement A Decrement register Decrement direct byte Decrement indirect RAM Increment Data Pointer (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED IN FO The MOVX instruction is typically used to access external data memory (Note: the C8051F320/1 does not support off-chip data or program memory). In the CIP-51, the MOVX write instruction is used to accesses external RAM (XRAM) and the on-chip program memory space implemented as re-programmable FLASH memory. The FLASH access feature provides a mechanism for the CIP-51 to update program code and use the program memory space for non-volatile data storage. Refer to Section "11. FLASH Memory" on page 105 for further details. RM Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock cycles as there are program bytes in the instruction. Conditional branch instructions take one less clock cycle to complete when the branch is not taken as opposed to when the branch is taken. Table 9.1 is the CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock cycles for each instruction. AT In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based solely on clock cycle timing. All instruction timings are specified in terms of clock cycles. IO N The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51TM instruction set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51 instructions are the binary and functional equivalent of their MCS-51TM counterparts, including opcodes, addressing modes and effect on PSW flags. However, instruction timing is different than that of the standard 8051. Page 73 C8051F320/1 Advanced Information Table 9.1. CIP-51 Instruction Set Summary Mnemonic MUL AB DIV AB DA A ANL A, Rn ANL A, direct ANL A, @Ri ANL A, #data ANL direct, A ANL direct, #data ORL A, Rn ORL A, direct ORL A, @Ri ORL A, #data ORL direct, A ORL direct, #data XRL A, Rn XRL A, direct XRL A, @Ri XRL A, #data XRL direct, A XRL direct, #data CLR A CPL A RL A RLC A RR A RRC A SWAP A Description Multiply A and B Divide A by B Decimal adjust A LOGICAL OPERATIONS AND Register to A AND direct byte to A AND indirect RAM to A AND immediate to A AND A to direct byte AND immediate to direct byte OR Register to A OR direct byte to A OR indirect RAM to A OR immediate to A OR A to direct byte OR immediate to direct byte Exclusive-OR Register to A Exclusive-OR direct byte to A Exclusive-OR indirect RAM to A Exclusive-OR immediate to A Exclusive-OR A to direct byte Exclusive-OR immediate to direct byte Clear A Complement A Rotate A left Rotate A left through Carry Rotate A right Rotate A right through Carry Swap nibbles of A DATA TRANSFER Move Register to A Move direct byte to A Move indirect RAM to A Move immediate to A Move A to Register Move direct byte to Register Move immediate to Register Move A to direct byte Move Register to direct byte Move direct byte to direct byte Move indirect RAM to direct byte Move immediate to direct byte Move A to indirect RAM Move direct byte to indirect RAM Move immediate to indirect RAM Bytes Clock Cycles 4 8 1 1 2 2 2 2 3 1 2 2 2 2 3 1 2 2 2 2 3 1 1 1 1 1 1 1 1 2 2 2 1 2 2 2 2 3 2 3 2 2 2 IO AT MOV A, Rn MOV A, direct MOV A, @Ri MOV A, #data MOV Rn, A MOV Rn, direct MOV Rn, #data MOV direct, A MOV direct, Rn MOV direct, direct MOV direct, @Ri MOV direct, #data MOV @Ri, A MOV @Ri, direct MOV @Ri, #data VA NC ED IN FO RM AD Page 74 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. N 1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 3 1 1 1 1 1 1 1 1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 1 1 1 Advanced Information C8051F320/1 Table 9.1. CIP-51 Instruction Set Summary Mnemonic MOV DPTR, #data16 MOVC A, @A+DPTR MOVC A, @A+PC MOVX A, @Ri MOVX @Ri, A MOVX A, @DPTR MOVX @DPTR, A PUSH direct POP direct XCH A, Rn XCH A, direct XCH A, @Ri XCHD A, @Ri CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C, bit ANL C, /bit ORL C, bit ORL C, /bit MOV C, bit MOV bit, C JC rel JNC rel JB bit, rel JNB bit, rel JBC bit, rel Description Load DPTR with 16-bit constant Move code byte relative DPTR to A Move code byte relative PC to A Move external data (8-bit address) to A Move A to external data (8-bit address) Move external data (16-bit address) to A Move A to external data (16-bit address) Push direct byte onto stack Pop direct byte from stack Exchange Register with A Exchange direct byte with A Exchange indirect RAM with A Exchange low nibble of indirect RAM with A BOOLEAN MANIPULATION Clear Carry Clear direct bit Set Carry Set direct bit Complement Carry Complement direct bit AND direct bit to Carry AND complement of direct bit to Carry OR direct bit to carry OR complement of direct bit to Carry Move direct bit to Carry Move Carry to direct bit Jump if Carry is set Jump if Carry is not set Jump if direct bit is set Jump if direct bit is not set Jump if direct bit is set and clear bit PROGRAM BRANCHING Absolute subroutine call Long subroutine call Return from subroutine Return from interrupt Absolute jump Long jump Short jump (relative address) Jump indirect relative to DPTR Jump if A equals zero Jump if A does not equal zero Compare direct byte to A and jump if not equal Compare immediate to A and jump if not equal Compare immediate to Register and jump if not equal Bytes 3 1 1 1 1 1 1 2 2 1 2 1 1 1 2 1 2 1 2 2 2 2 2 2 2 2 2 3 3 3 2 3 1 1 2 3 2 1 2 2 3 3 3 Clock Cycles 3 3 3 3 3 3 3 2 2 1 2 2 2 1 2 1 2 1 2 2 2 2 2 2 2 2/3 2/3 3/4 3/4 3/4 3 4 5 5 3 4 3 3 2/3 2/3 3/4 3/4 3/4 ACALL addr11 LCALL addr16 RET RETI AJMP addr11 LJMP addr16 SJMP rel JMP @A+DPTR JZ rel JNZ rel CJNE A, direct, rel CJNE A, #data, rel CJNE Rn, #data, rel (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED IN FO RM AT IO N Page 75 C8051F320/1 Advanced Information Table 9.1. CIP-51 Instruction Set Summary Mnemonic CJNE @Ri, #data, rel DJNZ Rn, rel DJNZ direct, rel NOP Description Compare immediate to indirect and jump if not equal Decrement Register and jump if not zero Decrement direct byte and jump if not zero No operation Bytes 3 2 3 1 Clock Cycles 4/5 2/3 3/4 1 Notes on Registers, Operands and Addressing Modes: Rn - Register R0-R7 of the currently selected register bank. @Ri - Data RAM location addressed indirectly through R0 or R1. rel - 8-bit, signed (two's complement) offset relative to the first byte of the following instruction. Used by SJMP and all conditional jumps. direct - 8-bit internal data location's address. This could be a direct-access Data RAM location (0x00-0x7F) or an SFR (0x80-0xFF). #data - 8-bit constant #data16 - 16-bit constant bit - Direct-accessed bit in Data RAM or SFR addr11 - 11-bit destination address used by ACALL and AJMP. The destination must be within the same 2K-byte page of program memory as the first byte of the following instruction. addr16 - 16-bit destination address used by LCALL and LJMP. The destination may be anywhere within the 8Kbyte program memory space. There is one unused opcode (0xA5) that performs the same function as NOP. All mnemonics copyrighted (c) Intel Corporation 1980. AD VA NC Page 76 ED IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM AT IO N Advanced Information 9.2. Memory Organization C8051F320/1 The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space but are accessed via different instruction types. The CIP-51 memory organization is shown in Figure 9.2. Figure 9.2. Memory Map PROGRAM/DATA MEMORY (FLASH) 0x3E00 0x3DFF RESERVED 0xFF 0x80 0x7F DATA MEMORY (RAM) INTERNAL DATA ADDRESS SPACE Upper 128 RAM (Indirect Addressing Only) (Direct and Indirect Addressing) RM 16K FLASH (In-System Programmable in 512 Byte Sectors) 0x30 0x2F 0x20 0x1F 0x00 Bit Addressable 0x0000 0xFFFF ED IN 0x0800 0x07FF 0x0400 0x03FF 0x0000 9.2.1. Program Memory The CIP-51 core has a 64k-byte program memory space. The C8051F320/1 implements 16k bytes of this program memory space as in-system, re-programmable FLASH memory, organized in a contiguous block from addresses 0x0000 to 0x3FFF. Addresses above 0x3DFF are reserved. (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD Program memory is normally assumed to be read-only. However, the CIP-51 can write to program memory by setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX instruction. This feature provides a mechanism for the CIP-51 to update program code and use the program memory space for non-volatile data storage. Refer to Section "11. FLASH Memory" on page 105 for further details. VA NC FO General Purpose Registers EXTERNAL DATA ADDRESS SPACE Same 2048 bytes as from 0x0000 to 0x07FF, wrapped on 2K-byte boundaries USB FIFOs 1024 Bytes XRAM - 1024 Bytes (accessable using MOVX instruction) AT Special Function Register's (Direct Addressing Only) IO Lower 128 RAM (Direct and Indirect Addressing) N Page 77 C8051F320/1 9.2.2. Data Memory Advanced Information 9.2.3. General Purpose Registers The MCS-51TM assembly language allows an alternate notation for bit addressing of the form XX.B where XX is the byte address and B is the bit position within the byte. For example, the instruction: MOV C, 22h.3 moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag. 9.2.5. Stack AD A programmer's stack can be located anywhere in the 256-byte data memory. The stack area is designated using the Stack Pointer (SP, 0x81) SFR. The SP will point to the last location used. The next value pushed on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to location 0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which is also the first register (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be initialized to a location in the data memory not being used for data storage. The stack depth can extend up to 256 bytes. VA NC Page 78 ED In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from 0x00 to 0x7F. Bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address 0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by the type of instruction used (bit source or destination operands as opposed to a byte source or destination). IN 9.2.4. Bit Addressable Locations DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of general-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1 (PSW.4), select the active register bank (see description of the PSW in Figure 9.6). This allows fast context switching when entering subroutines and interrupt service routines. Indirect addressing modes use registers R0 and R1 as index registers. RM AT The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the same address space as the Special Function Registers (SFR) but is physically separate from the SFR space. The addressing mode used by an instruction when accessing locations above 0x7F determines whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the upper 128 bytes of data memory. Figure 9.2 illustrates the data memory organization of the CIP-51. IO The CIP-51 includes 256 of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or as 128 bit locations accessible with the direct addressing mode. N Advanced Information 9.2.6. Special Function Registers C8051F320/1 Table 9.2. Special Function Register (SFR) Memory Map F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80 SPI0CN B ADC0CN ACC PCA0CN PSW TMR2CN SMB0CN IP P3 IE P2 SCON0 P1 TCON P0 0(8) PCA0L P0MDIN PCA0CPL1 XBR0 PCA0MD REF0CN REG0CN SMB0CF CLKMUL OSCXCN CLKSEL SPI0CFG SBUF0 TMR3CN TMOD SP 1(9) PCA0H PCA0CPL0 PCA0CPH0 PCA0CPL4 P1MDIN P2MDIN P3MDIN PCA0CPH1 PCA0CPL2 PCA0CPH2 PCA0CPL3 XBR1 IT01CF PCA0CPM0 PCA0CPM1 PCA0CPM2 PCA0CPM3 P0SKIP P1SKIP TMR2RLL TMR2RLH TMR2L TMR2H SMB0DAT ADC0GTL ADC0GTH ADC0LTL AMX0N AMX0P ADC0CF ADC0L OSCICN OSCICL EMI0CN SPI0CKR SPI0DAT P0MDOUT P1MDOUT CPT1CN CPT0CN CPT1MD CPT0MD TMR3RLL TMR3RLH TMR3L TMR3H TL0 TL1 TH0 TH1 DPL DPH 2(A) 3(B) 4(C) 5(D) PCA0CPH4 EIP1 PCA0CPH3 EIE1 PCA0CPM4 P2SKIP ADC0LTH ADC0H FLSCL P2MDOUT CPT1MX USB0ADR CKCON 6(E) VDM0CN EIP2 RSTSRC EIE2 USB0XCN IN FO RM AT The SFR registers are accessed anytime the direct addressing mode is used to access memory locations from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, SCON0, IE, etc.) are bit-addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate effect and should be avoided. Refer to the corresponding pages of the datasheet, as indicated in Table 9.3, for a detailed description of each register. IO N The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The CIP-51 duplicates the SFRs found in a typical 8051 implementation as well as implementing additional SFRs used to configure and access the sub-systems unique to the MCU. This allows the addition of new functionality while retaining compatibility with the MCS-51TM instruction set. Table 9.2 lists the SFRs implemented in the CIP-51 System Controller. FLKEY P3MDOUT CPT0MX USB0DAT PSCTL PCON 7(F) (bit addressable) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address Description ACC 0xE0 Accumulator ADC0CF 0xBC ADC0 Configuration ADC0CN 0xE8 ADC0 Control ADC0GTH 0xC4 ADC0 Greater-Than Compare High ADC0GTL 0xC3 ADC0 Greater-Than Compare Low ADC0H 0xBE ADC0 High ADC0L 0xBD ADC0 Low ADC0LTH 0xC6 ADC0 Less-Than Compare Word High AD VA NC Table 9.3. Special Function Registers Page 84 47 49 50 50 47 48 51 (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 ED Page 79 C8051F320/1 Advanced Information Table 9.3. Special Function Registers Register ADC0LTL AMX0N AMX0P B CKCON CLKSEL CPT0CN CPT0MD CPT0MX CPT1CN CPT1MD CPT1MX DPH DPL EIE1 EIE2 EIP1 EIP2 EMI0CN FLKEY FLSCL IE IP IT01CF OSCICL OSCICN OSCXCN P0 P0MDIN P0MDOUT P0SKIP P1 P1MDIN P1MDOUT P1SKIP P2 P2MDIN P2MDOUT P2SKIP P3 P3MDIN P3MDOUT PCA0CN PCA0CPH0 PCA0CPH1 PCA0CPH2 Address 0xC5 0xBA 0xBB 0xF0 0x8E 0xA9 0x9B 0x9D 0x9F 0x9A 0x9C 0x9E 0x83 0x82 0xE6 0xE7 0xF6 0xF7 0xAA 0xB7 0xB6 0xA8 0xB8 0xE4 0xB3 0xB2 0xB1 0x80 0xF1 0xA4 0xD4 0x90 0xF2 0xA5 0xD5 0xA0 0xF3 0xA6 0xD6 0xB0 0xF4 0xA7 0xD8 0xFC 0xEA 0xEC Description ADC0 Less-Than Compare Word Low AMUX0 Negative Channel Select AMUX0 Positive Channel Select B Register Clock Control Clock Select Comparator0 Control Comparator0 Mode Selection Comparator0 MUX Selection Comparator1 Control Comparator1 Mode Selection Comparator1 MUX Selection Data Pointer High Data Pointer Low Extended Interrupt Enable 1 Extended Interrupt Enable 2 Extended Interrupt Priority 1 Extended Interrupt Priority 2 External Memory Interface Control FLASH Lock and Key FLASH Scale Interrupt Enable Interrupt Priority INT0/INT1 Configuration Internal Oscillator Calibration Internal Oscillator Control External Oscillator Control Port 0 Latch Port 0 Input Mode Configuration Port 0 Output Mode Configuration Port 0 Skip Port 1 Latch Port 1 Input Mode Configuration Port 1 Output Mode Configuration Port 1 Skip Port 2 Latch Port 2 Input Mode Configuration Port 2 Output Mode Configuration Port 2 Skip Port 3 Latch Port 3 Input Mode Configuration Port 3 Output Mode Configuration PCA Control PCA Capture 0 High PCA Capture 1 High PCA Capture 2 High Page No. 51 46 45 84 221 123 60 62 61 63 65 64 82 82 90 92 91 92 113 109 109 88 89 93 117 117 120 133 133 134 134 135 135 136 136 137 137 138 138 139 139 140 244 248 248 248 AD VA NC Page 80 ED IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM AT IO N Advanced Information Table 9.3. Special Function Registers Register PCA0CPH3 PCA0CPH4 PCA0CPL0 PCA0CPL1 PCA0CPL2 PCA0CPL3 PCA0CPL4 PCA0CPM0 PCA0CPM1 PCA0CPM2 PCA0CPM3 PCA0CPM4 PCA0H PCA0L PCA0MD PCON PSCTL PSW REF0CN RSTSRC SBUF0 SCON0 SMB0CF SMB0CN SMB0DAT SP SPI0CFG SPI0CKR SPI0CN SPI0DAT TCON TH0 TH1 TL0 TL1 TMOD TMR2CN TMR2H TMR2L TMR2RLH TMR2RLL TMR3CN TMR3H TMR3L TMR3RLH TMR3RLL Address 0xEE 0xFE 0xFB 0xE9 0xEB 0xED 0xFD 0xDA 0xDB 0xDC 0xDD 0xDE 0xFA 0xF9 0xD9 0x87 0x8F 0xD0 0xD1 0xEF 0x99 0x98 0xC1 0xC0 0xC2 0x81 0xA1 0xA2 0xF8 0xA3 0x88 0x8C 0x8D 0x8A 0x8B 0x89 0xC8 0xCD 0xCC 0xCB 0xCA 0x91 0x95 0x94 0x93 0x92 Description PCA Capture 3High PCA Capture 4 High PCA Capture 0 Low PCA Capture 1 Low PCA Capture 2 Low PCA Capture 3Low PCA Capture 4 Low PCA Module 0 Mode Register PCA Module 1 Mode Register PCA Module 2 Mode Register PCA Module 3 Mode Register PCA Module 4 Mode Register PCA Counter High PCA Counter Low PCA Mode Power Control Program Store R/W Control Program Status Word Voltage Reference Control Reset Source Configuration/Status UART0 Data Buffer UART0 Control SMBus Configuration SMBus Control SMBus Data Stack Pointer SPI Configuration SPI Clock Rate Control SPI Control SPI Data Timer/Counter Control Timer/Counter 0 High Timer/Counter 1 High Timer/Counter 0 Low Timer/Counter 1 Low Timer/Counter Mode Timer/Counter 2 Control Timer/Counter 2 High Timer/Counter 2 Low Timer/Counter 2 Reload High Timer/Counter 2 Reload Low Timer/Counter 3Control Timer/Counter 3 High Timer/Counter 3Low Timer/Counter 3 Reload High Timer/Counter 3 Reload Low C8051F320/1 Page No. 248 248 248 248 248 248 248 246 246 246 246 246 247 247 245 95 108 83 56 102 197 196 180 182 184 83 208 210 209 211 219 222 222 222 222 220 226 227 227 227 227 231 232 232 232 232 (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED IN FO RM AT IO N Page 81 C8051F320/1 Advanced Information Table 9.3. Special Function Registers Reserved 9.2.7. Register Descriptions Figure 9.3. DPL: Data Pointer Low Byte R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 FO R/W Bit3 RM Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should not be set to logic l. Future product versions may use these bits to implement new features in which case the reset value of the bit will be logic 0, selecting the feature's default state. Detailed descriptions of the remaining SFRs are included in the sections of the datasheet associated with their corresponding system function. R/W Bit2 AT R/W Bit1 R/W Bit1 IO R/W Bit0 Reset Value Register Address VDM0CN 0xFF XBR0 0xE1 XBR1 0xE2 0x84-0x86, 0xAB-0xAF, 0xB4, 0xB5, 0xBF, 0xC7, 0xCE, 0xCF, 0xD2, 0xD3, 0xDF, 0xE3, 0xE5, 0xF5 N R/W Bit2 R/W Bit0 Description VDD Monitor Control Port I/O Crossbar Control 0 Port I/O Crossbar Control 1 Page No. 99 130 131 00000000 SFR Address: 0x82 Bits7-0: DPL: Data Pointer Low. The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly addressed memory. Figure 9.4. DPH: Data Pointer High Byte R/W Bit7 VA NC R/W Bit6 R/W Bit5 ED R/W Bit4 IN R/W Bit3 Reset Value 00000000 SFR Address: 0x83 Bits7-0: AD Page 82 DPH: Data Pointer High. The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly addressed memory. DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. Advanced Information Figure 9.5. SP: Stack Pointer C8051F320/1 N Bit0 R R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Reset Value 00000111 SFR Address: IO 0x81 Bits7-0: Figure 9.6. PSW: Program Status Word R/W R/W R/W R/W R/W RM R/W AT R/W SP: Stack Pointer. The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented before every PUSH operation. The SP register defaults to 0x07 after reset. Reset Value CY Bit7 AC Bit6 F0 Bit5 RS1 Bit4 RS0 Bit3 OV Bit2 F1 Bit1 PARITY Bit0 (bit addressable) 00000000 SFR Address: Bit7: Bit6: Bit5: Bits4-3: Bit2: Bit1: Bit0: OV: Overflow Flag. This bit is set to logic 1 if the last arithmetic operation resulted in a carry (addition), borrow (subtraction), or overflow (multiply or divide). It is cleared to logic 0 by all other arithmetic operations. F1: User Flag 1. This is a bit-addressable, general purpose flag for use under software control. PARITY: Parity Flag. This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum is even. (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC RS1 0 0 1 1 RS0 0 1 0 1 ED CY: Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow (subtraction). It is cleared to logic 0 by all other arithmetic operations. AC: Auxiliary Carry Flag This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow from (subtraction) the high order nibble. It is cleared to logic 0 by all other arithmetic operations. F0: User Flag 0. This is a bit-addressable, general purpose flag for use under software control. RS1-RS0: Register Bank Select. These bits select which register bank is used during register accesses. Register Bank 0 1 2 3 IN FO 0xD0 Address 0x00 - 0x07 0x08 - 0x0F 0x10 - 0x17 0x18 - 0x1F Page 83 C8051F320/1 Advanced Information Figure 9.7. ACC: Accumulator R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 N Bit0 R/W ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 00000000 SFR Address: Bits7-0: Figure 9.8. B: B Register R/W R/W R/W R/W R/W R/W RM AT R/W Reset Value ACC: Accumulator. This register is the accumulator for arithmetic operations. B.7 Bit7 B.6 Bit6 B.5 Bit5 B.4 Bit4 B.3 Bit3 B.2 Bit2 B.1 Bit1 IO (bit addressable) 0xE0 B.0 Bit0 (bit addressable) 00000000 SFR Address: 0xF0 Bits7-0: B: B Register. This register serves as a second accumulator for certain arithmetic operations. AD Page 84 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. VA NC ED IN FO Advanced Information 9.3. Interrupt Handler C8051F320/1 Each interrupt source can be individually enabled or disabled through the use of an associated interrupt enable bit in an SFR (IE-EIE2). However, interrupts must first be globally enabled by setting the EA bit (IE.7) to logic 1 before the individual interrupt enables are recognized. Setting the EA bit to logic 0 disables all interrupt sources regardless of the individual interrupt-enable settings. Some interrupt-pending flags are automatically cleared by the hardware when the CPU vectors to the ISR. However, most are not cleared by the hardware and must be cleared by software before returning from the ISR. If an interruptpending flag remains set after the CPU completes the return-from-interrupt (RETI) instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after the completion of the next instruction. 9.3.1. MCU Interrupt Sources and Vectors (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED The MCU supports 16 interrupt sources. Software can simulate an interrupt by setting any interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated and the CPU will vector to the ISR address associated with the interrupt-pending flag. MCU interrupt sources, associated vector addresses, priority order and control bits are summarized in Table 9.4 on page 87. Refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). IN FO RM AT If interrupts are enabled for the source, an interrupt request is generated when the interrupt-pending flag is set. As soon as execution of the current instruction is complete, the CPU generates an LCALL to a predetermined address to begin execution of an interrupt service routine (ISR). Each ISR must end with an RETI instruction, which returns program execution to the next instruction that would have been executed if the interrupt request had not occurred. If interrupts are not enabled, the interrupt-pending flag is ignored by the hardware and program execution continues as normal. (The interrupt-pending flag is set to logic 1 regardless of the interrupt's enable/disable state.) IO N The CIP-51 includes an extended interrupt system supporting a total of 16 interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripherals and external inputs pins varies according to the specific version of the device. Each interrupt source has one or more associated interrupt-pending flag(s) located in an SFR. When a peripheral or external source meets a valid interrupt condition, the associated interrupt-pending flag is set to logic 1. Page 85 C8051F320/1 9.3.2. External Interrupts Advanced Information 9.3.4. Interrupt Latency Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5 system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the ISR. If an interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL is made to service the pending interrupt. Therefore, the maximum response time for an interrupt (when no other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the CPU is performing an RETI instruction followed by a DIV as the next instruction. In this case, the response time is 18 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock cycles to execute the RETI, 8 clock cycles to complete the DIV instruction and 4 clock cycles to execute the LCALL to the ISR. If the CPU is executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the current ISR completes, including the RETI and following instruction. Note that the CPU is stalled during FLASH write/erase operations and USB FIFO MOVX accesses (see Section "12.2. Accessing USB FIFO Space" on page 112). Interrupt service latency will be increased for interrupts occuring while the CPU is stalled. The latency for these situations will be determined by the standard interrupt service procedure (as described above) and the amount of time the CPU is stalled. AD VA NC Each interrupt source can be individually programmed to one of two priority levels: low or high. A low priority interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP or EIP2) used to configure its priority level. Low priority is the default. If two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. If both interrupts have the same priority level, a fixed priority order is used to arbitrate, given in Table 9.4. Page 86 ED 9.3.3. Interrupt Priorities IN IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the /INT0 and /INT1 external interrupts, respectively. If an /INT0 or /INT1 external interrupt is configured as edge-sensitive, the corresponding interruptpending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as defined by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inactive. The external interrupt source must hold the input active until the interrupt request is recognized. It must then deactivate the interrupt request before execution of the ISR completes or another interrupt request will be generated. DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM /INT0 and /INT1 are assigned to Port pins as defined in the IT01CF register (see Figure 9.15). Note that /INT0 and /INT0 Port pin assignments are independent of any Crossbar assignments. /INT0 and /INT1 will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin via the Crossbar. To assign a Port pin only to /INT0 and/or /INT1, configure the Crossbar to skip the selected pin(s). This is accomplished by setting the associated bit in register XBR0 (see Section "14.1. Priority Crossbar Decoder" on page 127 for complete details on configuring the Crossbar). AT IT0 1 1 0 0 IN0PL 0 1 0 1 /INT0 Interrupt Active low, edge sensitive Active high, edge sensitive Active low, level sensitive Active high, level sensitive IT1 1 1 0 0 IN1PL 0 1 0 1 /INT1 Interrupt Active low, edge sensitive Active high, edge sensitive Active low, level sensitive Active high, level sensitive IO N The /INT0 and /INT1 external interrupt sources are configurable as active high or low, edge or level sensitive. The IN0PL (/INT0 Polarity) and IN1PL (/INT1 Polarity) bits in the IT01CF register select active high or active low; the IT0 and IT1 bits in TCON (Section "19.1. Timer 0 and Timer 1" on page 215) select level or edge sensitive. The table below lists the possible configurations. Advanced Information C8051F320/1 Table 9.4. Interrupt Summary Cleared by HW? Bit addressable? IO Y Y Y Y N N N N Interrupt Source Interrupt Vector Priority Pending Flag Order N Enable Flag Always Enabled ET0 (IE.1) ET1 (IE.3) ES0 (IE.4) ET2 (IE.5) ESPI0 (IE.6) Priority Control Reset External Interrupt 0 (/INT0) Timer 0 Overflow External Interrupt 1 (/INT1) Timer 1 Overflow UART0 Timer 2 Overflow 0x0000 0x0003 0x000B 0x0013 0x001B 0x0023 0x002B Top 0 1 2 3 4 5 None IE0 (TCON.1) TF0 (TCON.5) IE1 (TCON.3) AT Y Y Y Y Y Y Y Y N/A N/A Always Highest EX0 (IE.0) PX0 (IP.0) PT0 (IP.1) RM EX1 (IE.2) PX1 (IP.2) PT1 (IP.3) PS0 (IP.4) PT2 (IP.5) IN SPI0 0x0033 6 TF1 (TCON.7) RI0 (SCON0.0) TI0 (SCON0.1) TF2H (TMR2CN.7) TF2L (TMR2CN.6) SPIF (SPI0CN.7) WCOL (SPI0CN.6) MODF (SPI0CN.5) RXOVRN (SPI0CN.4) SI (SMB0CN.0) FO PSPI0 (IP.6) PSMB0 (EIP1.0) PUSB0 (EIP1.1) PWADC0 (EIP1.2) PADC0 (EIP1.3) PPCA0 (EIP1.4) PCP0 (EIP1.5) PCP1 (EIP1.6) PT3 (EIP1.7) PVBUS (EIP2.0) USB0 ADC0 Window Compare ADC0 Conversion Complete Programmable Counter Array Comparator0 Comparator1 0x0043 VA NC 0x0053 0x005B 0x0063 0x006B 0x0073 0x007B 0x004B Timer 3 Overflow VBUS Level AD (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 ED 8 9 10 11 12 13 14 15 SMB0 0x003B 7 ESMB0 (EIE1.0) EUSB0 Special N N (EIE1.1) AD0WINT EWADC0 Y N (ADC0CN.3) (EIE1.2) AD0INT EADC0 Y N (ADC0CN.5) (EIE1.3) CF (PCA0CN.7) EPCA0 Y N (EIE1.4) CCFn (PCA0CN.n) CP0FIF (CPT0CN.4) ECP0 N N CP0RIF (CPT0CN.5) (EIE1.5) CP1FIF (CPT1CN.4) ECP1 N N CP1RIF (CPT1CN.5) (EIE1.6) TF3H (TMR3CN.7) ET3 N N (EIE1.7) TF3L (TMR3CN.6) EVBUS N/A N/A N/A (EIE2.0) Page 87 C8051F320/1 9.3.5. Interrupt Register Descriptions Advanced Information The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). R/W R/W R/W R/W R/W R/W R/W Bit1 IO Figure 9.9. IE: Interrupt Enable N R/W Bit0 (bit addressable) Reset Value EA Bit7 ESPI0 Bit6 ET2 Bit5 ES0 Bit4 ET1 Bit3 EX1 Bit2 ET0 EX0 00000000 SFR Address: AT 0xA8 Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: AD EA: Enable All Interrupts. This bit globally enables/disables all interrupts. It overrides the individual interrupt mask settings. 0: Disable all interrupt sources. 1: Enable each interrupt according to its individual mask setting. ESPI0: Enable Serial Peripheral Interface (SPI0) Interrupt. This bit sets the masking of the SPI0 interrupts. 0: Disable all SPI0 interrupts. 1: Enable interrupt requests generated by SPI0. ET2: Enable Timer 2 Interrupt. This bit sets the masking of the Timer 2 interrupt. 0: Disable Timer 2 interrupt. 1: Enable interrupt requests generated by the TF2L or TF2H flags. ES0: Enable UART0 Interrupt. This bit sets the masking of the UART0 interrupt. 0: Disable UART0 interrupt. 1: Enable UART0 interrupt. ET1: Enable Timer 1 Interrupt. This bit sets the masking of the Timer 1 interrupt. 0: Disable all Timer 1 interrupt. 1: Enable interrupt requests generated by the TF1 flag. EX1: Enable External Interrupt 1. This bit sets the masking of External Interrupt 1. 0: Disable external interrupt 1. 1: Enable interrupt requests generated by the /INT1 input. ET0: Enable Timer 0 Interrupt. This bit sets the masking of the Timer 0 interrupt. 0: Disable all Timer 0 interrupt. 1: Enable interrupt requests generated by the TF0 flag. EX0: Enable External Interrupt 0. This bit sets the masking of External Interrupt 0. 0: Disable external interrupt 0. 1: Enable interrupt requests generated by the /INT0 input. VA NC Page 88 ED IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM Advanced Information Figure 9.10. IP: Interrupt Priority R/W R/W R/W R/W R/W R/W C8051F320/1 R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 N Bit0 - PSPI0 PT2 PS0 PT1 PX1 PT0 PX0 10000000 SFR Address: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED IN FO RM AT Page 89 Bit7: Bit6: UNUSED. Read = 1, Write = don't care. PSPI0: Serial Peripheral Interface (SPI0) Interrupt Priority Control. This bit sets the priority of the SPI0 interrupt. 0: SPI0 interrupt set to low priority level. 1: SPI0 interrupt set to high priority level. PT2: Timer 2 Interrupt Priority Control. This bit sets the priority of the Timer 2 interrupt. 0: Timer 2 interrupt set to low priority level. 1: Timer 2 interrupts set to high priority level. PS0: UART0 Interrupt Priority Control. This bit sets the priority of the UART0 interrupt. 0: UART0 interrupt set to low priority level. 1: UART0 interrupts set to high priority level. PT1: Timer 1 Interrupt Priority Control. This bit sets the priority of the Timer 1 interrupt. 0: Timer 1 interrupt set to low priority level. 1: Timer 1 interrupts set to high priority level. PX1: External Interrupt 1 Priority Control. This bit sets the priority of the External Interrupt 1 interrupt. 0: External Interrupt 1 set to low priority level. 1: External Interrupt 1 set to high priority level. PT0: Timer 0 Interrupt Priority Control. This bit sets the priority of the Timer 0 interrupt. 0: Timer 0 interrupt set to low priority level. 1: Timer 0 interrupt set to high priority level. PX0: External Interrupt 0 Priority Control. This bit sets the priority of the External Interrupt 0 interrupt. 0: External Interrupt 0 set to low priority level. 1: External Interrupt 0 set to high priority level. IO (bit addressable) 0xB8 C8051F320/1 Advanced Information Figure 9.11. EIE1: Extended Interrupt Enable 1 ET3 Bit7 ECP1 Bit6 ECP0 Bit5 EPCA0 Bit4 EADC0 Bit3 EWADC0 Bit2 EUSB0 Bit1 N ESMB0 Bit0 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 SFR Address: IO 0xE6 Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: AD VA NC ET3: Enable Timer 3 Interrupt. This bit sets the masking of the Timer 3 interrupt. 0: Disable Timer 3 interrupts. 1: Enable interrupt requests generated by the TF3L or TF3H flags. ECP1: Enable Comparator1 (CP1) Interrupt. This bit sets the masking of the CP1 interrupt. 0: Disable CP1 interrupts. 1: Enable interrupt requests generated by the CP1RIF or CP1FIF flags. ECP0: Enable Comparator0 (CP0) Interrupt. This bit sets the masking of the CP0 interrupt. 0: Disable CP0 interrupts. 1: Enable interrupt requests generated by the CP0RIF or CP0FIF flags. EPCA0: Enable Programmable Counter Array (PCA0) Interrupt. This bit sets the masking of the PCA0 interrupts. 0: Disable all PCA0 interrupts. 1: Enable interrupt requests generated by PCA0. EADC0: Enable ADC0 Conversion Complete Interrupt. This bit sets the masking of the ADC0 Conversion Complete interrupt. 0: Disable ADC0 Conversion Complete interrupt. 1: Enable interrupt requests generated by the AD0INT flag. EWADC0: Enable Window Comparison ADC0 Interrupt. This bit sets the masking of ADC0 Window Comparison interrupt. 0: Disable ADC0 Window Comparison interrupt. 1: Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT). EUSB0: Enable USB0 Interrupt. This bit sets the masking of the USB0 interrupt. 0: Disable all USB0 interrupts. 1: Enable interrupt requests generated by USB0. ESMB0: Enable SMBus (SMB0) Interrupt. This bit sets the masking of the SMB0 interrupt. 0: Disable all SMB0 interrupts. 1: Enable interrupt requests generated by SMB0. Page 90 ED IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM AT Advanced Information C8051F320/1 Figure 9.12. EIP1: Extended Interrupt Priority 1 PT3 Bit7 PCP1 Bit6 PCP0F Bit5 PPCA0 Bit4 PADC0 Bit3 PWADC0 Bit2 PUSB0 Bit1 N PSMB0 Bit0 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 SFR Address: IO 0xF6 Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC PT3: Timer 3 Interrupt Priority Control. This bit sets the priority of the Timer 3 interrupt. 0: Timer 3 interrupts set to low priority level. 1: Timer 3 interrupts set to high priority level. PCP1: Comparator1 (CP1) Interrupt Priority Control. This bit sets the priority of the CP1 interrupt. 0: CP1 interrupt set to low priority level. 1: CP1 interrupt set to high priority level. PCP0: Comparator0 (CP0) Interrupt Priority Control. This bit sets the priority of the CP0 interrupt. 0: CP0 interrupt set to low priority level. 1: CP0 interrupt set to high priority level. PPCA0: Programmable Counter Array (PCA0) Interrupt Priority Control. This bit sets the priority of the PCA0 interrupt. 0: PCA0 interrupt set to low priority level. 1: PCA0 interrupt set to high priority level. PADC0 ADC0 Conversion Complete Interrupt Priority Control. This bit sets the priority of the ADC0 Conversion Complete interrupt. 0: ADC0 Conversion Complete interrupt set to low priority level. 1: ADC0 Conversion Complete interrupt set to high priority level. PWADC0: ADC0 Window Comparator Interrupt Priority Control. This bit sets the priority of the ADC0 Window interrupt. 0: ADC0 Window interrupt set to low priority level. 1: ADC0 Window interrupt set to high priority level. PUSB0: USB0 Interrupt Priority Control. This bit sets the priority of the USB0 interrupt. 0: USB0 interrupt set to low priority level. 1: USB0 interrupt set to high priority level. PSMB0: SMBus (SMB0) Interrupt Priority Control. This bit sets the priority of the SMB0 interrupt. 0: SMB0 interrupt set to low priority level. 1: SMB0 interrupt set to high priority level. ED IN FO RM AT Page 91 C8051F320/1 Advanced Information Figure 9.13. EIE2: Extended Interrupt Enable 2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 N Bit0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value EVBUS 00000000 SFR Address: IO - 0xE7 Figure 9.14. EIP2: Extended Interrupt Priority 2 R/W R/W R/W R/W FO R/W RM R/W AT R/W Bit1 Reset Value Bits7-1: Bit0: UNUSED. Read = 0000000b. Write = don't care. EVBUS: Enable VBUS Level Interrupt. This bit sets the masking of the VBUS interrupt. 0: Disable all VBUS interrupts. 1: Enable interrupt requests generated by VBUS level sense. Bit7 Bit6 Bit5 Bit4 - Bit2 PVBUS Bit0 00000000 SFR Address: Bit3 0xF7 Bits7-1: Bit0: AD Page 92 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. VA NC ED UNUSED. Read = 0000000b. Write = don't care. PVBUS: VBUS Level Interrupt Priority Control. This bit sets the priority of the VBUS interrupt. 0: VBUS interrupt set to low priority level. 1: VBUS interrupt set to high priority level. IN Advanced Information C8051F320/1 Figure 9.15. IT01CF: INT0/INT1 Configuration Register IN1PL Bit7 IN1SL2 Bit6 IN1SL1 Bit5 IN1SL0 Bit4 IN0PL Bit3 IN0SL2 Bit2 IN0SL1 Bit1 N IN0SL0 Bit0 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000001 SFR Address: IO 0xE4 Note: Refer to Figure 19.4 for INT0/1 edge- or level-sensitive interrupt selection. Bit7: Bits6-4: Bit3: Bits2-0: IN0SL2-0 000 001 010 011 100 101 110 111 (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC IN0PL: /INT0 Polarity 0: /INT0 interrupt is active low. 1: /INT0 interrupt is active high. INT0SL2-0: /INT0 Port Pin Selection Bits These bits select which Port pin is assigned to /INT0. Note that this pin assignment is independent of the Crossbar. /INT0 will monitor the assigned Port pin without disturbing the peripheral that has been assigned the Port pin via the Crossbar. The Crossbar will not assign the Port pin to a peripheral if it is configured to skip the selected pin (accomplished by setting to `1' the corresponding bit in register P0SKIP). /INT0 Port Pin P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 ED IN1SL2-0 000 001 010 011 100 101 110 111 /INT1 Port Pin P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 IN FO RM IN1PL: /INT1 Polarity 0: /INT1 input is active low. 1: /INT1 input is active high. IN1SL2-0: /INT1 Port Pin Selection Bits These bits select which Port pin is assigned to /INT1. Note that this pin assignment is independent of the Crossbar; /INT1 will monitor the assigned Port pin without disturbing the peripheral that has been assigned the Port pin via the Crossbar. The Crossbar will not assign the Port pin to a peripheral if it is configured to skip the selected pin (accomplished by setting to `1' the corresponding bit in register P0SKIP). AT Page 93 C8051F320/1 9.4. Power Management Modes Advanced Information The internal oscillator can be placed in Suspend mode (see Section "13. Oscillators" on page 115). In Suspend mode, the internal oscillator is stopped until a non-idle USB event is detected, or the VBUS input signal matches the polarity selected by the VBPOL bit in register REG0CN (Figure 8.5 on Page 70). 9.4.1. Idle Mode Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon as the instruction that sets the bit completes execution. All internal registers and memory maintain their original data. All analog and digital peripherals can remain active during Idle mode. Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume operation. The pending interrupt will be serviced and the next instruction to be executed after the return from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit. If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence and begins program execution at address 0x0000. If enabled, the Watchdog Timer (WDT) will eventually cause an internal watchdog reset and thereby terminate the Idle mode. This feature protects the system from an unintended permanent shutdown in the event of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by software prior to entering the Idle mode if the WDT was initially configured to allow this operation. This provides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefinitely, waiting for an external stimulus to wake up the system. Refer to Section "10.6. PCA Watchdog Timer Reset" on page 100 for more information on the use and configuration of the WDT. 9.4.2. Stop Mode If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode. The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the MCD timeout of 100 sec. AD Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruction that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all digital peripherals are stopped; the state of the external oscillator circuit is not affected. Each analog peripheral (including the external oscillator circuit) may be shut down individually prior to entering Stop Mode. Stop mode can only be terminated by an internal or external reset. On reset, the CIP-51 performs the normal reset sequence and begins program execution at address 0x0000. VA NC Page 94 ED IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM AT Although the CIP-51 has Idle and Stop modes built in (as with any standard 8051 architecture), power management of the entire MCU is better accomplished through system clock and individual peripheral management. Each analog peripheral can be disabled when not in use and placed in low power mode. Digital peripherals, such as timers or serial buses, draw little power when they are not in use. Turning off the oscillators lowers power consumption considerably; however a reset is required to restart the MCU. IO The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the CPU while leaving the peripherals and clocks active. In Stop mode, the CPU is halted, all interrupts, are inactive, and the internal oscillator is stopped (analog peripherals remain in their selected states; the external oscillator is not affected). Since clocks are running in Idle mode, power consumption is dependent upon the system clock frequency and the number of peripherals left in active mode before entering Idle. Stop mode consumes the least power. Figure 1.15 describes the Power Control Register (PCON) used to control the CIP-51's power management modes. N Advanced Information C8051F320/1 Figure 9.16. PCON: Power Control Register R/W R/W R/W R/W R/W R/W R/W N R/W Bit0 Reset Value GF5 Bit7 GF4 Bit6 GF3 Bit5 GF2 Bit4 GF1 Bit3 GF0 Bit2 STOP Bit1 IDLE 00000000 SFR Address: IO 0x87 Bit1: Bit0: (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED IN FO RM AT Bits7-2: GF5-GF0: General Purpose Flags 5-0. These are general purpose flags for use under software control. STOP: Stop Mode Select. Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0. 1: CPU goes into Stop mode (internal oscillator stopped). IDLE: Idle Mode Select. Setting this bit will place the CIP-51 in Idle mode. This bit will always be read as 0. 1: CPU goes into Idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, Serial Ports, and Analog Peripherals are still active.) Page 95 C8051F320/1 Advanced Information Notes AD VA NC Page 96 ED IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM AT IO N Advanced Information 10. RESET SOURCES C8051F320/1 Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: * * * * CIP-51 halts program execution Special Function Registers (SFRs) are initialized to their defined reset values External Port pins are forced to a known state Interrupts and timers are disabled. Figure 10.1. Reset Sources IN VDD ED FO Supply Monitor + - On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the internal oscillator. Refer to Section "13. Oscillators" on page 115 for information on selecting and configuring the system clock source. The Watchdog Timer is enabled with the system clock divided by 12 as its clock source (Section "20.3. Watchdog Timer Mode" on page 242 details the use of the Watchdog Timer). Program execution begins at location 0x0000. RM Enable Power On Reset The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pull-ups are enabled during and after the reset. For VDD Monitor and Power-On Resets, the /RST pin is driven low until the device exits the reset state. AT '0' USB Controller All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal data memory are unaffected during a reset; any previously stored data is preserved. However, since the stack pointer SFR is reset, the stack is effectively lost even though the data on the stack is not altered. IO Enable N (wired-OR) Px.x Px.x Comparator 0 + - /RST VA NC C0RSEF Missing Clock Detector (oneshot) EN PCA WDT Reset Funnel Software Reset (SWRSF) EN AD Clock Multiplier System Clock MCD Enable WDT Enable Internal Oscillator Errant FLASH Operation XTAL1 XTAL2 External Oscillator Drive CIP-51 Microcontroller Core Extended Interrupt Handler VBUS Transition System Reset Clock Select (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 Page 97 C8051F320/1 10.1. Power-On Reset Advanced Information Software can force a power-on reset by writing `1' to the PINRSF bit in register RSTSRC. RM Figure 10.2. Power-On and VDD Monitor Reset Timing volts VDD 2.70 2.4 2.0 VRST 1.0 IN FO VD D AT VDD Monitor Reset On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other resets). Since all resets cause program execution to begin at the same location (0x0000) software can read the PORSF flag to determine if a power-up was the cause of reset. The content of internal data memory should be assumed to be undefined after a power-on reset. The VDD monitor is enabled following a power-on reset. IO ED Logic HIGH /RST Logic LOW TPORDelay AD VA NC Power-On Reset Page 98 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. N t During power-up, the device is held in a reset state and the /RST pin is driven low until VDD settles above VRST. A Power-On Reset delay (TPORDelay) occurs before the device is released from reset; this delay is typically less than 0.3 ms. Figure 10.2. plots the power-on and VDD monitor reset timing. Advanced Information 10.2. Power-Fail Reset / VDD Monitor C8051F320/1 See Figure 10.2 for VDD monitor timing. See Table 10.1 for complete electrical characteristics of the VDD monitor. Figure 10.3. VDM0CN: VDD Monitor Control R/W Bit7 R Bit6 R Bit5 R R R Bit2 R R Reset Value Bit4 IN VDMEN VDDSTAT Reserved Reserved Reserved Bit3 FO RM Reserved Step 1. Enable the VDD monitor (VDM0CN.7 = `1'). Step 2. Wait for the VDD monitor to stabilize (see Table 10.1 for the VDD Monitor turn-on time). Step 3. Select the VDD monitor as a reset source (RSTSRC.1 = `1'). AT Reserved Bit1 Important Note: The VDD monitor must be enabled before it is selected as a reset source. Selecting the VDD monitor as a reset source before it is enabled and stabilized will cause a system reset. The procedure for configuring the VDD monitor as a reset source is shown below: IO When a power-down transition or power irregularity causes VDD to drop below VRST, the power supply monitor will drive the /RST pin low and hold the CIP-51 in a reset state (see Figure 10.2). When VDD returns to a level above VRST, the CIP-51 will be released from the reset state. Note that even though internal data memory contents are not altered by the power-fail reset, it is impossible to determine if VDD dropped below the level required for data retention. If the PORSF flag reads `1', the data may no longer be valid. The VDD monitor is enabled after power-on resets; however its defined state (enabled/disabled) is not altered by any other reset source. For example, if the VDD monitor is enabled and a software reset is performed, the VDD monitor will still be enabled after the reset. N Bit0 Reserved Variable SFR Address: 0xFF Bit6: Bits5-0: (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED Bit7: VDMEN: VDD Monitor Enable. This bit turns the VDD monitor circuit on/off. The VDD Monitor cannot generate system resets until it is also selected as a reset source in register RSTSRC (Figure 10.4). The VDD Monitor must be allowed to stabilize before it is selected as a reset source. Selecting the VDD monitor as a reset source before it has stabilized will generate a system reset. See Table 10.1 for the minimum VDD Monitor turn-on time. The VDD Monitor is enabled following all POR resets. 0: VDD Monitor Disabled. 1: VDD Monitor Enabled. VDDSTAT: VDD Status. This bit indicates the current power supply status (VDD Monitor output). 0: VDD is at or below the VDD monitor threshold. 1: VDD is above the VDD monitor threshold. Reserved. Read = Variable. Write = don't care. Page 99 C8051F320/1 10.3. External Reset Advanced Information 10.4. Missing Clock Detector Reset If a FLASH read/write/erase or program read targets an illegal address, a system reset is generated. This may occur due to any of the following: * * * * A FLASH write or erase is attempted above user code space. This occurs when PSWE is set to `1' and a MOVX write operation is attempted above address 0x3DFF. A FLASH read is attempted above user code space. This occurs when a MOVC operation is attempted above address 0x3DFF. A Program read is attempted above user code space. This occurs when user code attempts to branch to an address above 0x3DFF. A FLASH read, write or erase attempt is restricted due to a FLASH security setting (see Section "11.3. Security Options" on page 107). The FERROR bit (RSTSRC.6) is set following a FLASH error reset. The state of the /RST pin is unaffected by this reset. AD VA NC 10.7. FLASH Error Reset Page 100 ED The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be used to prevent software from running out of control during a system malfunction. The PCA WDT function can be enabled or disabled by software as described in Section "20.3. Watchdog Timer Mode" on page 242; the WDT is enabled and clocked by SYSCLK / 12 following any reset. If a system malfunction prevents user software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is set to `1'. The state of the /RST pin is unaffected by this reset. IN 10.6. PCA Watchdog Timer Reset DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO Comparator0 can be configured as a reset source by writing a `1' to the C0RSEF flag (RSTSRC.5). Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on chatter on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-inverting input voltage (on CP0+) is less than the inverting input voltage (on CP0-), a system reset is generated. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read `1' signifying Comparator0 as the reset source; otherwise, this bit reads `0'. The state of the /RST pin is unaffected by this reset. RM 10.5. Comparator0 Reset AT The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If more than 100 s pass between rising edges on the system clock, the one-shot will time out and generate a reset. After a MCD reset, the MCDRSF flag (RSTSRC.2) will read `1', signifying the MCD as the reset source; otherwise, this bit reads `0'. Writing a `1' to the MCDRSF bit enables the Missing Clock Detector; writing a `0' disables it. The state of the /RST pin is unaffected by this reset. IO N The external /RST pin provides a means for external circuitry to force the device into a reset state. Asserting an active-low signal on the /RST pin generates a reset; an external pull-up and/or decoupling of the /RST pin may be necessary to avoid erroneous noise-induced resets. See Table 10.1 for complete /RST pin specifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset. Advanced Information 10.8. Software Reset C8051F320/1 Software may force a reset by writing a `1' to the SWRSF bit (RSTSRC.4). The SWRSF bit will read `1' following a software forced reset. The state of the /RST pin is unaffected by this reset. 10.9. USB Reset 1. 2. The USBRSF bit will read `1' following a USB reset. The state of the /RST pin is unaffected by this reset. (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED IN FO RM AT RESET signaling is detected on the USB network. The USB Function Controller (USB0) must be enabled for RESET signaling to be detected. See Section "15. Universal Serial Bus Controller (USB0)" on page 141 for information on the USB Function Controller. The voltage on the VBUS pin matches the polarity selected by the VBPOL bit in register REG0CN. See Section "8. Voltage Regulator (REG0)" on page 67 for details on the VBUS detection circuit. IO Writing `1' to the USBRSF bit in register RSTSRC selects USB0 as a reset source. With USB0 selected as a reset source, a system reset will be generated when either of the following occur: N Page 101 C8051F320/1 Advanced Information Figure 10.4. RSTSRC: Reset Source Register R/W R R/W R/W R Bit3 R/W Bit2 R/W R/W Reset Value USBRSF Bit7 FERROR Bit6 C0RSEF Bit5 SWRSF Bit4 WDTRSF MCDRSF PORSF Bit1 PINRSF Variable SFR Address: N Bit0 0xEF Bit7: Bit6: Bit4: Bit3: Bit2: Bit0: AD Note: For bits that act as both reset source enables (on a write) and reset indicator flags (on a read), readmodify-write instructions read and modify the source enable only. This applies to bits: USBRSF, C0RSEF, SWRSF, MCDRSF, PORSF, PINRSF. VA NC Page 102 ED Bit1: IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM Bit5: USBRSF: USB Reset Flag 0: Read: Last reset was not a USB reset; Write: USB resets disabled. 1: Read: Last reset was a USB reset; Write: USB resets enabled. FERROR: FLASH Error Indicator. 0: Source of last reset was not a FLASH read/write/erase error. 1: Source of last reset was a FLASH read/write/erase error. C0RSEF: Comparator0 Reset Enable and Flag. 0: Read: Source of last reset was not Comparator0; Write: Comparator0 is not a reset source. 1: Read: Source of last reset was Comparator0; Write: Comparator0 is a reset source (active-low). SWRSF: Software Reset Force and Flag. 0: Read: Source of last reset was not a write to the SWRSF bit; Write: No Effect. 1: Read: Source of last was a write to the SWRSF bit; Write: Forces a system reset. WDTRSF: Watchdog Timer Reset Flag. 0: Source of last reset was not a WDT timeout. 1: Source of last reset was a WDT timeout. MCDRSF: Missing Clock Detector Flag. 0: Read: Source of last reset was not a Missing Clock Detector timeout; Write: Missing Clock Detector disabled. 1: Read: Source of last reset was a Missing Clock Detector timeout; Write: Missing Clock Detector enabled; triggers a reset if a missing clock condition is detected. PORSF: Power-On / VDD Monitor Reset Flag. This bit is set anytime a power-on reset occurs. Writing this bit selects/deselects the VDD monitor as a reset source. Note: writing `1' to this bit before the VDD monitor is enabled and stabilized can cause a system reset. See register VDM0CN (Figure 10.3). 0: Read: Last reset was not a power-on or VDD monitor reset; Write: VDD monitor is not a reset source. 1: Read: Last reset was a power-on or VDD monitor reset; all other reset flags indeterminate; Write: VDD monitor is a reset source. PINRSF: HW Pin Reset Flag. 0: Read: Source of last reset was not /RST pin; Write: No effect. 1: Read: Source of last reset was /RST pin; Write: Forces a Power-On Reset. /RST is driven low. AT IO Advanced Information C8051F320/1 Table 10.1. Reset Electrical Characteristics /RST Input High Voltage /RST Input Low Voltage /RST Input Pull-Up Current VDD POR Threshold (VRST) Missing Clock Detector Timeout Reset Time Delay Minimum /RST Low Time to Generate a System Reset VDD Monitor Turn-on Time /RST = 0.0 V IO 25 2.55 220 0.7 x VDD N -40C to +85C unless otherwise specified. PARAMETER CONDITIONS IOL = 8.5 mA, VDD = 2.7 V to 3.6 V /RST Output Low Voltage MIN TYP MAX 0.6 UNITS V V AT 2.40 100 5.0 15 100 0.3 x VDD 40 2.70 500 A V s s s s (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED IN FO RM Time from last system clock rising edge to reset initiation Delay between release of any reset source and code execution at location 0x0000 Page 103 C8051F320/1 Advanced Information Notes AD VA NC Page 104 ED IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM AT IO N Advanced Information 11. FLASH MEMORY C8051F320/1 The simplest means of programming the FLASH memory is through the C2 interface using programming tools provided by Cygnal or a third party vendor. This is the only means for programming a non-initialized device. For details on the C2 commands to program FLASH memory, see Section "21. C2 Interface" on page 249. To ensure the integrity of FLASH contents, it is strongly recommended that the on-chip VDD Monitor be enabled in any system that includes code that writes and/or erases FLASH memory from software. 11.1.1. FLASH Lock and Key Functions A write to FLASH memory can clear bits to logic 0 but cannot set them; only an erase operation can set bits to logic 1 in FLASH. A byte location to be programmed must be erased before a new value is written. The FLASH memory is organized in 512-byte pages. The erase operation applies to an entire page (setting all bytes in the page to 0xFF). To erase an entire 512-byte page, perform the following steps: Step 1. Disable interrupts (recommended). Step 2. Write the first key code to FLKEY: 0xA5. Step 3. Write the second key code to FLKEY: 0xF1. Step 4. Set the PSEE bit (register PSCTL). Step 5. Set the PSWE bit (register PSCTL). Step 6. Using the MOVX instruction, write a data byte to any location within the 512-byte page to be erased. Step 7. Clear the PSWE bit (register PSCTL). Step 8. Clear the PSEE bit (register PSCTI). (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC The FLASH memory can be programmed by software using the MOVX write instruction with the address and data byte to be programmed provided as normal operands. Before writing to FLASH memory using MOVX, FLASH write operations must be enabled by: (1) Writing the FLASH key codes in sequence to the FLASH Lock register (FLKEY); and (2) Setting the PSWE Program Store Write Enable bit (PSCTL.0) to logic 1 (this directs the MOVX writes to target FLASH memory). The PSWE bit remains set until cleared by software. ED 11.1.2. FLASH Erase Procedure IN FLASH writes and erases by user software are protected with a lock and key function. The FLASH Lock and Key Register (FLKEY) must be written with the correct key codes, in sequence, before FLASH operations may be performed. The key codes are: 0xA5, 0xF1. The timing does not matter, but the codes must be written in order. If the key codes are written out of order, or the wrong codes are written, FLASH writes and erases will be disabled until the next system reset. FLASH writes and erases will also be disabled if a FLASH write or erase is attempted before the key codes have been written properly. The FLASH lock resets after each write or erase; the key codes must be written again before a following FLASH operation can be performed. The FLKEY register is detailed in Figure 11.3. FO RM AT 11.1. Programming The FLASH Memory IO On-chip, re-programmable FLASH memory is included for program code and non-volatile data storage. The FLASH memory can be programmed in-system, a single byte at a time, through the C2 interface or by software using the MOVX instruction. Once cleared to logic 0, a FLASH bit must be erased to set it back to logic 1. FLASH bytes would typically be erased (set to 0xFF) before being reprogrammed. The write and erase operations are automatically timed by hardware for proper execution; data polling to determine the end of the write/erase operation is not required. Code execution is stalled during a FLASH write/erase operation. Refer to Table 11.1 for complete FLASH memory electrical characteristics. N Page 105 C8051F320/1 11.1.3. FLASH Write Procedure Advanced Information FLASH bytes are programmed by software with the following sequence: Step 1. Disable interrupts (recommended). Step 2. Erase the 512-byte FLASH page containing the target location, as described in Section 11.1.2. Step 3. Write the first key code to FLKEY: 0xA5. Step 4. Write the second key code to FLKEY: 0xF1. Step 5. Set the PSWE bit (register PSCTL). Step 6. Clear the PSEE bit (register PSCTL). Step 7. Using the MOVX instruction, write a single data byte to the desired location within the 512-byte sector. Step 8. Clear the PSWE bit (register PSCTL). Steps 3-8 must be repeated for each byte to be written. After FLASH writes are complete, PSWE should be cleared so that MOVX instructions do not target program memory. Table 11.1. FLASH Electrical Characteristics FO PARAMETER FLASH Size Endurance Erase Cycle Time Write Cycle Time CONDITIONS C8051F320/1 25 MHz System Clock 25 MHz System Clock RM MIN 20k 10 40 16384 AT TYP 100k 15 55 IO 20 70 N MAX UNITS bytes Erase/Write ms s AD Page 106 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. VA NC ED IN Note: 512 bytes at location 0x3E00 to 0x3FFF are reserved. Advanced Information 11.2. Non-volatile Data Storage C8051F320/1 The FLASH memory can be used for non-volatile data storage as well as program code. This allows data such as calibration coefficients to be calculated and stored at run time. Data is written using the MOVX write instruction and read using the MOVC instruction. Note: MOVX read instructions always target XRAM. 11.3. Security Options A Security Lock Byte located at the last byte of FLASH user space offers protection of the FLASH program memory from access (reads, writes, or erases) by unprotected code or the C2 interface. The FLASH security mechanism allows the user to lock n 512-byte FLASH pages, starting at page 0 (addresses 0x0000 to 0x01FF), where n is the 1's compliment number represented by the Security Lock Byte. See example below. Security Lock Byte: 1's Compliment: FLASH pages locked: Addresses locked: 11111101b 00000010b 2 0x0000 to 0x03FF Important Notes About the FLASH Security: 1. 2. 3. 4. 5. 6. 7. (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC Clearing any bit of the Lock Byte to `0' will lock the FLASH page containing the Lock Byte (in addition to the selected pages). Locked pages cannot be read, written, or erased via the C2 interface. Locked pages cannot be read, written, or erased by user firmware executing from unlocked memory space. User firmware executing in a locked page may read and write FLASH memory in any locked or unlocked page excluding the reserved area. User firmware executing in a locked page may erase FLASH memory in any locked or unlocked page excluding the reserved area and the page containing the Lock Byte. Locked pages can only be erased through the C2 interface with a C2 Device Erase command. If a user firmware FLASH access attempt is denied (per restrictions #3, #4, and #5 above), a FLASH Error system reset will be generated. ED IN FO RM AT The CIP-51 provides security options to protect the FLASH memory from inadvertent modification by software as well as to prevent the viewing of proprietary program code and constants. The Program Store Write Enable (bit PSWE in register PSCTL) and the Program Store Erase Enable (bit PSEE in register PSCTL) bits protect the FLASH memory from accidental modification by software. PSWE must be explicitly set to `1' before software can modify the FLASH memory; both PSWE and PSEE must be set to `1' before software can erase FLASH memory. Additional security features prevent proprietary program code and data constants from being read or altered across the C2 interface. IO N Page 107 C8051F320/1 Advanced Information Figure 11.1. FLASH Program Memory Map and Security Byte C8051F320/1 Reserved 0x3E00 Locked when any other FLASH pages are locked Lock Byte 0x3DFF 0x3DFE 0x3C00 Unlocked FLASH Pages Access limit set according to the FLASH security lock byte Figure 11.2. PSCTL: Program Store R/W Control R/W R/W R/W R/W IN FO R/W RM 0x0000 R/W AT R/W IO FLASH memory organized in 512-byte pages N R/W Reset Value Bit7 Bit6 Bit5 - - Reserved Bit2 PSEE Bit1 PSWE Bit0 00000000 SFR Address: Bit4 Bit3 Bit0: AD VA NC Bits7-3: Bit2: Bit1: Unused: Read = 00000b. Write = don't care. Reserved. Read = 0b. Must Write = 0b. PSEE: Program Store Erase Enable Setting this bit (in combination with PSWE) allows an entire page of FLASH program memory to be erased. If this bit is logic 1 and FLASH writes are enabled (PSWE is logic 1), a write to FLASH memory using the MOVX instruction will erase the entire page that contains the location addressed by the MOVX instruction. The value of the data byte written does not matter. 0: FLASH program memory erasure disabled. 1: FLASH program memory erasure enabled. PSWE: Program Store Write Enable Setting this bit allows writing a byte of data to the FLASH program memory using the MOVX write instruction. The FLASH location should be erased before writing data. 0: Writes to FLASH program memory disabled. 1: Writes to FLASH program memory enabled; the MOVX write instruction targets FLASH memory. Page 108 ED 0x8F DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. Advanced Information C8051F320/1 Figure 11.3. FLKEY: FLASH Lock and Key Register N Bit0 R/W R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Reset Value 00000000 SFR Address: IO 0xB7 Bits7-0: Figure 11.4. FLSCL: FLASH Scale Register R/W R/W R/W R/W Bit4 R/W Bit3 R/W R/W Reset Value Bit7 Bit6 Bit5 ED FOSE Reserved Reserved Reserved IN Reserved FO FLKEY: FLASH Lock and Key Register Write: This register must be written to before FLASH writes or erases can be performed. FLASH remains locked until this register is written to with the following key codes: 0xA5, 0xF1. The timing of the writes does not matter, as long as the codes are written in order. The key codes must be written for each FLASH write or erase operation. FLASH will be locked until the next system reset if the wrong codes are written or if a FLASH operation is attempted before the codes have been written correctly. Read: When read, bits 1-0 indicate the current FLASH lock state. 00: FLASH is write/erase locked. 01: The first key code has been written (0xA5). 10: FLASH is unlocked (writes/erases allowed). 11: FLASH writes/erases disabled until the next reset. RM Reserved Bit2 AT Bit1 Reserved Reserved Bit0 10000000 SFR Address: 0xB6 Bits6-0: (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC Bits7: FOSE: FLASH One-shot Enable This bit enables the FLASH read one-shot. When the FLASH one-shot disabled, the FLASH sense amps are enabled for a full clock cycle during FLASH reads. At system clock frequencies below 10 MHz, disabling the FLASH one-shot will increase system power consumption. 0: FLASH one-shot disabled. 1: FLASH one-shot enabled. RESERVED. Read = 0. Must Write 0. Page 109 C8051F320/1 Advanced Information Notes AD VA NC Page 110 ED IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM AT IO N Advanced Information 12. EXTERNAL RAM C8051F320/1 The C8051F320/1 devices include 2048 bytes of on-chip XRAM. This XRAM space is split into user RAM (addresses 0x0000 - 0x03FF) and USB0 FIFO space (addresses 0x0400 - 0x07FF). 0xFFFF Same 2048 bytes as from 0x0000 to 0x07FF, wrapped on 2K-byte boundaries 0x0800 0x07FF 0x0400 0x03FF 0x0000 XRAM 1024 Bytes 12.1. Accessing User XRAM (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC Important Note: The upper 1k of the 2k XRAM functions as USB FIFO space. See Section 12.2 for details on accessing this memory space. ED For any of the addressing modes the upper 5 bits of the 16-bit external data memory address word are "don't cares". As a result, the 2048-byte RAM is mapped modulo style over the entire 64k external data memory address range. For example, the XRAM byte at address 0x0000 is also at address 0x0800, 0x1000, 0x1800, 0x2000, etc. IN XRAM can be accessed using the external move instruction (MOVX) and the data pointer (DPTR), or using MOVX indirect addressing mode. If the MOVX instruction is used with an 8-bit address operand (such as @R1), then the high byte of the 16-bit address is provided by the External Memory Interface Control Register (EMI0CN as shown in Figure 12.3). Note: the MOVX instruction is also used for writes to the FLASH memory. See Section "11. FLASH Memory" on page 105 for details. The MOVX instruction accesses XRAM by default. FO RM USB FIFOs 1024 Bytes Accessed through USB FIFO registers Accessed with the MOVX instruction AT IO Page 111 N Figure 12.1. External Ram Memory Map C8051F320/1 12.2. Accessing USB FIFO Space Advanced Information Unused areas of the FIFO space may be used as general purpose XRAM, accessible as described in Section 12.1. The FIFO block operates on the USB clock domain; thus the USB clock must be active when accessing FIFO space. Note that the number of SYSCLK cycles required by the MOVX instruction is increased when accessing USB FIFO space. Important Note: The USB clock must be active when accessing FIFO space. 0x03FF FO User XRAM Space (System Clock Domain) IN RM 0x07FF 0x07C0 0x07BF 0x0740 0x073F 0x0640 0x063F 0x0440 0x043F 0x0400 Figure 12.2. XRAM Memory Map Expanded View AT Endpoint0 (64 bytes) Endpoint1 (128 bytes) Endpoint2 (256 bytes) Endpoint3 (512 bytes) Free (64 bytes) User XRAM (1024 bytes) IO AD VA NC 0x0000 Page 112 ED DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. N The upper 1k of XRAM functions as USB FIFO space. Figure 12.2 shows an expanded view of the FIFO space and user XRAM. FIFO space is accessed via USB FIFO registers; see Section "15.5. FIFO Management" on page 149 for more information on accessing these FIFOs. The MOVX instruction should not be used to load or modify USB data in the FIFO space. USB FIFO Space (USB Clock Domain) Advanced Information C8051F320/1 Figure 12.3. EMI0CN: External Memory Interface Control Bit7 Bit6 Bit5 Bit4 Bit3 PGSEL2 Bit2 PGSEL1 Bit1 N Bit0 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value PGSEL0 00000000 SFR Address: IO 0xAA (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED IN FO RM AT Bits7-3: Bits2-0: Not Used - reads 00000b. PGSEL[2:0]: XRAM Page Select Bits. The XRAM Page Select Bits provide the high byte of the 16-bit external data memory address when using an 8-bit MOVX command, effectively selecting a 256-byte page of RAM. The upper 5-bits are "don't cares", so the 2k address blocks are repeated modulo over the entire 64k external data memory address space. Page 113 C8051F320/1 Advanced Information Notes AD VA NC Page 114 ED IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM AT IO N Advanced Information 13. OSCILLATORS C8051F320/1 Figure 13.1. Oscillator Diagram OSCICL Option 2 VDD Option 3 XTAL2 OSCICN IOSCEN IFRDY SUSPEND IFCN1 IFCN0 AT x2 x2 Clock Multiplier MULSEL1 MULSEL0 USBCLK2 USBCLK1 USBCLK0 IO CLKSEL CLKSL1 CLKSL0 SYSCLK IOSC / 2 EXOSC USBCLK EXOSC / 2 EXOSC / 3 EXOSC / 4 USBCLK2-0 XTAL2 EN Programmable Internal Clock Generator XTAL1 10M XTAL2 XTLVLD Input Circuit OSC IOSC Option 4 XTAL2 ED XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 VA NC OSCXCN 13.1. Programmable Internal Oscillator All C8051F320/1 devices include a programmable internal oscillator that defaults as the system clock after a system reset. The internal oscillator period can be programmed via the OSCICL register as defined by Equation 13.1, where fBASE is the frequency of the internal oscillator following a reset, T is the change in internal oscillator period, and OSCICL is a change to the value held in register OSCICL. AD Equation 13.1. Typical Change in Internal Oscillator Period with OSCICL 1 T 0.0025 x ------------ x OSCICL f BASE (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 MULEN MULINIT MULRDY XFCN2 XFCN1 XFCN0 IN FO EXOSC IOSC EXOSC EXOSC / 2 Option 1 CLKMUL RM n N C8051F320/1 devices include a programmable internal oscillator, an external oscillator drive circuit, and a 4x Clock Multiplier. The internal oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as shown in Figure 13.1. The system clock (SYSCLK) can be derived from the internal oscillator, external oscillator circuit, or the 4x Clock Multiplier divided by 2. The USB clock (USBCLK) can be derived from the internal oscillator, external oscillator, or 4x Clock Multiplier. Oscillator electrical specifications are given in Table 13.3 on page 124. Page 115 C8051F320/1 Advanced Information Important Note: Once the internal oscillator frequency has been modified, the internal oscillator may not be used as the USB clock as described in Section 13.4. The internal oscillator frequency will reset to its original factory-calibrated frequency following any device reset, at which point the oscillator is suitable for use as the USB clock. Software should read and adjust the value of OSCICL according to Equation 13.1 to obtain the desired frequency. The example below shows how to obtain an 11.6 MHz internal oscillator frequency. fBASE is the internal oscillator reset frequency; TBASE is the reset oscillator period. fDES is the desired internal oscillator frequency; TDES is the desired oscillator period. The required change in period (TDES) is the difference between the base period and the desired period. 1 1 -9 T DES = ----------------------- - ----------------------- = 2.87 x 10 s 11600000 12000000 Using Equation 13.1 and the above calculations, find OSCICL: 2.87 x 10 -9 OSCICL = 13.79 Important Note: If the sum of the reset value of OSCICL and OSCICL is greater than 31 or less than 0, then the device will not be capable of producing the desired frequency. 13.1.2. Internal Oscillator Suspend Mode The internal oscillator may be placed in Suspend mode by writing `1' to the SUSPEND bit in register OSCICN. In Suspend mode, the internal oscillator is stopped until a non-idle USB event is detected (Section 15) or VBUS matches the polarity selected by the VBPOL bit in register REG0CN (Section 8.2). Note that the USB transceiver must be enabled for a USB event to be detected. AD OSCICL is rounded to the nearest integer (14) and added to the reset value of register OSCICL. VA NC 1 = 0.0025 x ------------ x OSCICL f BASE Page 116 ED IN f BASE = 12000000Hz 1 T BASE = ----------------------- s 12000000 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO f DES = 11600000Hz 1 T DES = ----------------------- s 11600000 RM AT The OSCICL reset value is factory calibrated to result in a 12 MHz internal oscillator with a 1.5% accuracy; this frequency is suitable for use as the USB clock (see Section 13.4). Software may modify the frequency of the internal oscillator as described below. IO 13.1.1. Programming the Internal Oscillator on C8051F320/1 Devices N On C8051F320/1 devices, OSCICL is factory calibrated to obtain a 12 MHz base frequency (fBASE). Section 13.1.1 details oscillator programming for C8051F320/1 devices. Electrical specifications for the precision internal oscillator are given in Table 13.3 on page 124. Note that the system clock may be derived from the programmed internal oscillator divided by 1, 2, 4, or 8, as defined by the IFCN bits in register OSCICN. The divide value defaults to 8 following a reset. Advanced Information C8051F320/1 Figure 13.2. OSCICN: Internal Oscillator Control Register R/W R R/W R R/W R/W R/W N R/W Bit0 Reset Value IOSCEN Bit7 IFRDY Bit6 SUSPEND Bit5 Bit4 Bit3 Bit2 IFCN1 Bit1 IFCN0 00010100 SFR Address: IO 0xB2 Bit6: Bit5: R/W R/W R/W ED R/W Bit4 Figure 13.3. OSCICL: Internal Oscillator Calibration Register R/W Bit3 R/W R/W Bit1 R/W Bit0 Reset Value Bit7 VA NC - - - IN FO Bits4-2: Bits1-0: RM OSCCAL Bit2 AT Bit7: IOSCEN: Internal Oscillator Enable Bit. 0: Internal Oscillator Disabled. 1: Internal Oscillator Enabled. IFRDY: Internal Oscillator Frequency Ready Flag. 0: Internal Oscillator is not running at programmed frequency. 1: Internal Oscillator is running at programmed frequency. SUSPEND: Force Suspend Writing a `1' to this bit will force the internal oscillator to be stopped. The oscillator will be re-started on the next non-idle USB event (i.e., RESUME signaling) or VBUS interrupt event (see Figure 8.5). UNUSED. Read = 000b, Write = don't care. IFCN1-0: Internal Oscillator Frequency Control Bits. 00: SYSCLK derived from Internal Oscillator divided by 8. 01: SYSCLK derived from Internal Oscillator divided by 4. 10: SYSCLK derived from Internal Oscillator divided by 2. 11: SYSCLK derived from Internal Oscillator divided by 1. 00010000 SFR Address: Bit6 Bit5 0xB3 Bits4-0: OSCCAL: Oscillator Calibration Value These bits determine the internal oscillator period as per Equation 13.1. Note: The contents of this register are undefined when Clock Recovery is enabled. See Section "15.4. USB Clock Configuration" on page 148 for details on Clock Recovery. (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD Page 117 C8051F320/1 13.2. Advanced Information External Oscillator Drive Circuit 13.2.1. Clocking Timers Directly Through the External Oscillator 13.2.2. External Crystal Example If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 13.1, Option 1. The External Oscillator Frequency Control value (XFCN) should be chosen from the Crystal column of the table in Figure 13.4 (OSCXCN register). For example, a 12 MHz crystal requires an XFCN setting of 111b. When the crystal oscillator is first enabled, the oscillator amplitude detection circuit requires a settling time to achieve proper bias. Introducing a delay of 1 ms between enabling the oscillator and checking the XTLVLD bit will prevent a premature switch to the external oscillator as the system clock. Switching to the external oscillator before the crystal oscillator has stabilized can result in unpredictable behavior. The recommended procedure is: Step 1. Step 2. Step 3. Step 4. Enable the external oscillator. Wait at least 1 ms. Poll for XTLVLD => `1'. Switch the system clock to the external oscillator. Important Note on External Crystals: Crystal oscillator circuits are quite sensitive to PCB layout. The crystal should be placed as close as possible to the XTAL pins on the device. The traces should be as short as possible and shielded with ground plane from any other traces which could introduce noise or interference. AD VA NC Page 118 ED IN The external oscillator source divided by eight is a clock option for the timers (Section "19. Timers" on page 215) and the Programmable Counter Array (PCA) (Section "20. Programmable Counter Array (PCA0)" on page 233). When the external oscillator is used to clock these peripherals, but is not used as the system clock, the external oscillator frequency must be less than or equal to the system clock frequency. In this configuration, the clock supplied to the peripheral (external oscillator / 8) is synchronized with the system clock; the jitter associated with this synchronization is limited to 0.5 system clock cycles. DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM Important Note on External Oscillator Usage: Port pins must be configured when using the external oscillator circuit. When the external oscillator drive circuit is enabled in crystal/resonator mode, Port pins P0.2 and P0.3 are used as XTAL1 and XTAL2 respectively. When the external oscillator drive circuit is enabled in capacitor, RC, or CMOS clock mode, Port pin P0.3 is used as XTAL2. The Port I/O Crossbar should be configured to skip the Port pins used by the oscillator circuit; see Section "14.1. Priority Crossbar Decoder" on page 127 for Crossbar configuration. Additionally, when using the external oscillator circuit in crystal/resonator, capacitor, or RC mode, the associated Port pins should be configured as analog inputs. In CMOS clock mode, the associated pin should be configured as a digital input. See Section "14.2. Port I/O Initialization" on page 129 for details on Port input mode selection. AT IO The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor, or RC network. A CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crystal/resonator must be wired across the XTAL1 and XTAL2 pins as shown in Option 1 of Figure 13.1. A 10 M resistor also must be wired across the XTAL1 and XTAL2 pins for the crystal/resonator configuration. In RC, capacitor, or CMOS clock configuration, the clock source should be wired to the XTAL2 pin as shown in Option 2, 3, or 4 of Figure 13.1. The type of external oscillator must be selected in the OSCXCN register, and the frequency control bits (XFCN) must be selected appropriately (see Figure 13.4) N Advanced Information 13.2.3. External RC Example C8051F320/1 f = 1.23( 103 ) / RC = 1.23 ( 103 ) / [ 246 * 50 ] = 0.1 MHz = 100 kHz 13.2.4. External Capacitor Example f = KF / ( C * VDD ) = KF / ( 50 * 3 ) MHz f = KF / 150 MHz If a frequency of roughly 150 kHz is desired, select the K Factor from the table in Figure 13.4 as KF = 22: f = 22 / 150 = 0.146 MHz, or 146 kHz Therefore, the XFCN value to use in this example is 011b. (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED IN FO RM If a capacitor is used as an external oscillator for the MCU, the circuit should be configured as shown in Figure 13.1, Option 3. The capacitor should be no greater than 100 pF; however for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To determine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, select the capacitor to be used and find the frequency of oscillation from the equations below. Assume VDD = 3.0 V and C = 50 pF: AT Referring to the table in Figure 13.4, the required XFCN setting is 010b. Programming XFCN to a higher setting in RC mode will improve frequency accuracy at an increased external oscillator supply current. IO N If an RC network is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 13.1, Option 2. The capacitor should be no greater than 100 pF; however for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To determine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, first select the RC network value to produce the desired frequency of oscillation. If the frequency desired is 100 kHz, let R = 246 k and C = 50 pF: Page 119 C8051F320/1 Advanced Information Figure 13.4. OSCXCN: External Oscillator Control Register R Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R R/W R/W R/W Reset Value XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 Bit3 XFCN2 Bit2 XFCN1 Bit1 N XFCN0 Bit0 00000000 SFR Address: IO AT 0xB1 Bit7: Bits6-4: Bit3: Bits2-0: CRYSTAL MODE (Circuit from Figure 13.1, Option 1; XOSCMD = 11x) Choose XFCN value to match crystal or resonator frequency. RC MODE (Circuit from Figure 13.1, Option 2; XOSCMD = 10x) Choose XFCN value to match frequency range: f = 1.23(103) / (R * C), where f = frequency of clock in MHz C = capacitor value in pF R = Pull-up resistor value in k C MODE (Circuit from Figure 13.1, Option 3; XOSCMD = 10x) Choose K Factor (KF) for the oscillation frequency desired: f = KF / (C * VDD), where f = frequency of clock in MHz C = capacitor value the XTAL2 pin in pF VDD = Power Supply on MCU in volts AD VA NC XFCN 000 001 010 011 100 101 110 111 Crystal (XOSCMD = 11x) f 32kHz 32kHz < f 84kHz 84kHz < f 225kHz 225kHz < f 590kHz 590kHz < f 1.5MHz 1.5MHz < f 4MHz 4MHz < f 10MHz 10MHz < f 30MHz IN FO XTLVLD: Crystal Oscillator Valid Flag. (Read only when XOSCMD = 11x.) 0: Crystal Oscillator is unused or not yet stable. 1: Crystal Oscillator is running and stable. XOSCMD2-0: External Oscillator Mode Bits. 00x: External Oscillator circuit off. 010: External CMOS Clock Mode. 011: External CMOS Clock Mode with divide by 2 stage. 100: RC Oscillator Mode. 101: Capacitor Oscillator Mode. 110: Crystal Oscillator Mode. 111: Crystal Oscillator Mode with divide by 2 stage. RESERVED. Read = 0, Write = don't care. XFCN2-0: External Oscillator Frequency Control Bits. 000-111: See table below: RC (XOSCMD = 10x) f 25kHz 25kHz < f 50kHz 50kHz < f 100kHz 100kHz < f 200kHz 200kHz < f 400kHz 400kHz < f 800kHz 800kHz < f 1.6MHz 1.6MHz < f 3.2MHz RM C (XOSCMD = 10x) K Factor = 0.87 K Factor = 2.6 K Factor = 7.7 K Factor = 22 K Factor = 65 K Factor = 180 K Factor = 664 K Factor = 1590 Page 120 ED DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. Advanced Information 13.3. 4x Clock Multiplier C8051F320/1 The 4x Clock Multiplier is configured via the CLKMUL register. The procedure for configuring and enabling the 4x Clock Multiplier is as follows: 1. 2. 3. 4. 5. 6. Reset the Multiplier by writing 0x00 to register CLKMUL. Select the Multiplier input source via the MULSEL bits. Enable the Multiplier with the MULEN bit (CLKMUL | = 0x80). Delay for >5 s. Initialize the Multiplier with the MULINIT bit (CLKMUL | = 0xC0). Poll for MULRDY => `1'. Important Note: When using an external oscillator as the input to the 4x Clock Multiplier, the external source must be enabled and stable before the Multiplier is initialized. See Section 13.4 for details on selecting an external oscillator source. Figure 13.5. CLKMUL: Clock Multiplier Control Register R/W R/W Bit6 R Bit5 R/W IN FO R/W RM R/W AT R/W Bit1 R/W Bit0 Reset Value MULEN Bit7 MULINIT MULRDY - - Bit2 IO MULSEL N The 4x Clock Multiplier allows a 12 MHz oscillator to generate the 48 MHz clock required for Full Speed USB communication (see Section "15.4. USB Clock Configuration" on page 148). A divided version of the Multiplier output can also be used as the system clock. See Section 13.4 for details on system clock and USB clock source selection. 00000000 SFR Address Bit4 Bit3 Bit7: Bit6: Bit5: AD Bits4-2: Bits1-0: MULEN: Clock Multiplier Enable 0: Clock Multiplier disabled. 1: Clock Multiplier enabled. MULINIT: Clock Multiplier Initialize This bit should be a `0' when the Clock Multiplier is enabled. Once enabled, writing a `1' to this bit will initialize the Clock Multiplier. The MULRDY bit reads `1' when the Clock Multiplier is stabilized. MULRDY: Clock Multiplier Ready This read-only bit indicates the status of the Clock Multiplier. 0: Clock Multiplier not ready. 1: Clock Multiplier ready (locked). Unused. Read = 000b; Write = don't care. MULSEL: Clock Multiplier Input Select These bits select the clock supplied to the Clock Multiplier. VA NC MULSEL 00 01 10 11 (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 ED 0xB9 Selected Clock Internal Oscillator External Oscillator External Oscillator / 2 RESERVED Page 121 C8051F320/1 13.4. Advanced Information System and USB Clock Selection 13.4.1. System Clock Selection 13.4.2. USB Clock Selection Some example USB clock configurations for Full and Low Speed mode are given below: Table 13.1. Typical USB Full Speed Clock Settings Internal Oscillator ED Clock Signal USB Clock Clock Multiplier Input Internal Oscillator Input Source Selection Clock Multiplier IN FO The USBCLK[2:0] bits in register CLKSEL select which oscillator source is used as the USB clock. The USB clock may be derived from the 4x Clock Multiplier output, a divided version of the internal oscillator, or a divided version of the external oscillator. Note that the USB clock must be 48 MHz when operating USB0 as a Full Speed Function; the USB clock must be 6 MHz when operating USB0 as a Low Speed Function. See Figure 13.6 for USB clock selection options. Clock Signal USB Clock Clock Multiplier Input External Oscillator Clock VA NC Internal Oscillator Divide by 1 External Oscillator Input Source Selection Clock Multiplier External Oscillator Crystal Oscillator Mode 12 MHz Crystal Recovery must be enabled for this configuration. AD Table 13.2. Typical USB Low Speed Clock Settings Internal Oscillator Input Source Selection Internal Oscillator / 2 Divide by 1 External Oscillator Input Source Selection External Oscillator / 4 Crystal Oscillator Mode 24 MHz Crystal Register Bit Settings USBCLK = 001b IFCN = 11b Register Bit Settings USBCLK = 101b XOSCMD = 110b XFCN = 111b Clock Signal USB Clock Internal Oscillator Clock Signal USB Clock External Oscillator Page 122 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. RM The CLKSL[1:0] bits in register CLKSEL select which oscillator source is used as the system clock. CLKSL[1:0] must be set to 01b for the system clock to run from the external oscillator; however the external oscillator may still clock certain peripherals (timers, PCA, USB) when the internal oscillator is selected as the system clock. The system clock may be switched on-the-fly between the internal oscillator, external oscillator, and 4x Clock Multiplier so long as the selected oscillator is enabled and has settled. AT IFCN = 11b Register Bit Settings USBCLK = 000b MULSEL = 00b Register Bit Settings USBCLK = 000b MULSEL = 01b XOSCMD = 110b XFCN = 111b IO The internal oscillator requires little start-up time and may be selected as the system or USB clock immediately following the OSCICN write that enables the internal oscillator. External crystals and ceramic resonators typically require a start-up time before they are settled and ready for use. The Crystal Valid Flag (XTLVLD in register OSCXCN) is set to `1' by hardware when the external oscillator is settled. To avoid reading a false XTLVLD, in crystal mode software should delay at least 1 ms between enabling the external oscillator and checking XTLVLD. RC and C modes typically require no startup time. N Advanced Information C8051F320/1 Figure 13.6. CLKSEL: Clock Select Register R/W R/W Bit6 R/W R/W Bit4 R/W R/W R/W Bit1 N R/W Bit0 Reset Value Bit7 USBCLK Bit5 Bit3 Bit2 CLKSL 00000000 SFR Address IO 0xA9 Bits3-2: Bits1-0: CLKSL 00 01 10 11 (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED Unused. Read = 00b; Write = don't care. CLKSL1-0: System Clock Select These bits select the system clock source. IN USBCLK 000 001 010 011 100 101 110 111 Selected Clock 4x Clock Multiplier Internal Oscillator / 2 External Oscillator External Oscillator / 2 External Oscillator / 3 External Oscillator / 4 RESERVED RESERVED Selected Clock Internal Oscillator (as determined by the IFCN bits in register OSCICN) External Oscillator 4x Clock Multiplier / 2 RESERVED FO RM AT Bit 7: Bits6-4: Unused. Read = 0b; Write = don't care. USBCLK2-0: USB Clock Select These bits select the clock supplied to USB0. When operating USB0 in full-speed mode, the selected clock should be 48 MHz. When operating USB0 in low-speed mode, the selected clock should be 6 MHz. Page 123 C8051F320/1 Advanced Information Table 13.3. Oscillator Electrical Characteristics -40C to +85C unless otherwise specified PARAMETER Internal Oscillator Frequency Internal Oscillator Supply Current (from VDD) USB Clock Frequency Applies OSCICN.7 = 1 Full Speed Mode Low Speed Mode 47.88 5.91 IO 450 48 6 N 48.12 6.09 CONDITIONS Reset Frequency MIN 11.82 TYP 12 MAX 12.18 UNITS MHz A MHz only to external oscillator sources. AD VA NC Page 124 ED DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. IN FO RM AT Advanced Information 14. PORT INPUT/OUTPUT C8051F320/1 Figure 14.1. Port I/O Functional Block Diagram Highest Priority UART SPI 2 4 2 2 2 IN FO Priority Decoder XBR0, XBR1, PnSKIP Registers RM 8 8 8 1 All Port I/Os are 5 V tolerant (refer to Figure 14.2 for the Port cell circuit). The Port I/O cells are configured as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1,2,3). Complete Electrical Specifications for Port I/O are given in Table 14.1 on page 140. AT P0 I/O Cells P1 I/O Cells P2 I/O Cells P3 I/O Cells The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder (Figure 14.3 and Figure 14.4). The registers XBR0 and XBR1, defined in Figure 14.5 and Figure 14.6, are used to select internal digital functions. PnMDOUT, PnMDIN Registers IO Digital and analog resources are available through 25 I/O pins (C8051F320) or 21 I/O pins (C8051F321). Port pins are organized as shown in Figure 14.1. Each of the Port pins can be defined as general-purpose I/O (GPIO) or analog input; Port pins P0.0-P2.3 can be assigned to one of the internal digital resources as shown in Figure 14.3. The designer has complete control over which functions are assigned, limited only by the number of physical I/O pins. This resource assignment flexibility is achieved through the use of a Priority Crossbar Decoder. Note that the state of a Port I/O pin can always be read in the corresponding Port latch, regardless of the Crossbar settings. N P0.0 P0.7 P1.0 P1.7 P2.0 P2.7 P3.0 (Internal Digital Signals) SMBus CP0 Outputs CP1 Outputs ED Digital Crossbar Lowest Priority VA NC SYSCLK PCA 6 2 8 T0, T1 Note: P2.4-P2.7 only available on the C8051F320 P0 (P0.0-P0.7) 8 (P1.0-P1.7) 8 (P2.0-P2.7) 8 AD (Port Latches) P1 P2 P3 (P3.0) (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 Page 125 C8051F320/1 Advanced Information Figure 14.2. Port I/O Cell Block Diagram /WEAK-PULLUP PUSH-PULL /PORT-OUTENABLE VDD VDD IO (WEAK) Analog Select GND PORT-OUTPUT ANALOG INPUT PORT-INPUT AD VA NC Page 126 ED IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM AT N PORT PAD Advanced Information 14.1. Priority Crossbar Decoder C8051F320/1 Figure 14.3. Crossbar Priority Decoder with No Pins Skipped P0 CNVSTR XTAL1 XTAL2 VREF P1 P2 SF Signals PIN I/O TX0 RX0 SCK MISO MOSI NSS SDA SCL CP0 CP0A CP1 CP1A SYSCLK CEX0 CEX1 CEX2 CEX3 CEX4 ECI T0 T1 0 1 2 3 4 5 6 7 0 1 FO 2 3 4 RM 5 6 Important Note on Crossbar Configuration: If a Port pin is claimed by a peripheral without use of the Crossbar, its corresponding PnSKIP bit should be set. This applies to P0.7 if VREF is used, P0.3 and/or P0.2 if the external oscillator circuit is enabled, P0.6 if the ADC is configured to use the external conversion start signal (CNVSTR), and any selected ADC or Comparator inputs. The Crossbar skips selected pins as if they were already assigned, and moves to the next unassigned pin. Figure 14.3 shows the Crossbar Decoder priority with no Port pins skipped (P0SKIP, P1SKIP, P2SKIP = 0x00); Figure 14.4 shows the Crossbar Decoder priority with the XTAL1 (P0.2) and XTAL2 (P0.3) pins skipped (P0SKIP = 0x0C). AT 7 0 1 0 0 0 0 IO 2 0 P2SKIP[0:3] The Priority Crossbar Decoder (Figure 14.3) assigns a priority to each I/O function, starting at the top with UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that resource (excluding UART0, which is always at pins 4 and 5). If a Port pin is assigned, the Crossbar skips that pin when assigning the next selected resource. Additionally, the Crossbar will skip Port pins whose associated bits in the PnSKIP registers are set. The PnSKIP registers allow software to skip Port pins that are to be used for analog input, dedicated functions, or GPIO. N 3 0 4 5 6 7 VA NC ED IN AD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0SKIP[0:7] P1SKIP[0:7] Port pin potentially available to peripheral SF Signals Special Function Signals are not assigned by the Crossbar. When these signals are enabled, the Crossbar must be manually configured to skip their corresponding port pins. (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 Signals Unavailable Page 127 C8051F320/1 Advanced Information Figure 14.4. Crossbar Priority Decoder with Crystal Pins Skipped CNVSTR XTAL1 XTAL2 PIN I/O TX0 RX0 SCK MISO MOSI NSS SDA SCL CP0 CP0A CP1 CP1A SYSCLK CEX0 CEX1 CEX2 CEX3 CEX4 ECI T0 T1 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 IO 1 2 0 0 P2SKIP[0:3] SF Signals VREF N 3 4 5 6 7 P0 P1 P2 RM 0 0 1 1 0 0 AT ED 0 0 IN 0 0 0 0 0 0 0 0 0 0 P0SKIP[0:7] P1SKIP[0:7] Port pin potentially available to peripheral SF Signals Special Function Signals are not assigned by the Crossbar. When these signals are enabled, the Crossbar must be manually configured to skip their corresponding port pins. Important Note: The SPI can be operated in either 3-wire or 4-wire modes, depending on the state of the NSSMD1NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not be routed to a Port pin. AD Registers XBR0 and XBR1 are used to assign the digital I/O resources to the physical I/O Port pins. Note that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus (SDA and SCL); when the UART is selected, the Crossbar assigns both pins associated with the UART (TX and RX). UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned to P0.4; UART RX0 is always assigned to P0.5. Standard Port I/Os appear contiguously after the prioritized functions have been assigned. VA NC Page 128 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. Signals Unavailable FO Advanced Information 14.2. Port I/O Initialization Port I/O initialization consists of the following steps: C8051F320/1 Important Note: The Crossbar must be enabled to use Ports P0, P1, and P2.0-P2.3 as standard Port I/O in output mode. These Port output drivers are disabled while the Crossbar is disabled. P2.4-P2.7 and P3.0 always function as standard GPIO. (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC Registers XBR0 and XBR1 must be loaded with the appropriate values to select the digital I/O functions required by the design. Setting the XBARE bit in XBR1 to `1' enables the Crossbar. Until the Crossbar is enabled, the external pins remain as standard Port I/O (in input mode), regardless of the XBRn Register settings. For given XBRn Register settings, one can determine the I/O pin-out using the Priority Decode Table; as an alternative, the Configuration Wizard utility of the Cygnal IDE software will determine the Port I/O pin-assignments based on the XBRn Register settings. ED The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMDOUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is required even for the digital resources selected in the XBRn registers, and is not automatic. The only exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the PnMDOUT settings. When the WEAKPUD bit in XBR1 is `0', a weak pull-up is enabled for all Port I/O configured as open-drain. WEAKPUD does not affect the push-pull Port I/O. Furthermore, the weak pull-up is turned off on an output that is driving a `0' to avoid unnecessary power dissipation. IN FO Additionally, all analog input pins should be configured to be skipped by the Crossbar (accomplished by setting the associated bits in PnSKIP). Port input mode is set in the PnMDIN register, where a `1' indicates a digital input, and a `0' indicates an analog input. All pins default to digital inputs on reset. See Figure 14.8 for the PnMDIN register details. RM All Port pins must be configured as either analog or digital inputs. Any pins to be used as Comparator or ADC inputs should be configured as an analog inputs. When a pin is configured as an analog input, its weak pull-up, digital driver, and digital receiver are disabled. This process saves power and reduces noise on the analog input. Pins configured as digital inputs may still be used by analog peripherals; however this practice is not recommended. To configure a Port pin for digital input, write `0' to the corresponding bit in register PnMDOUT, and write `1' to the corresponding Port latch (register Pn). AT Step 1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (PnMDIN). Step 2. Select the output mode (open-drain or push-pull) for all Port pins, using the Port Output Mode register (PnMDOUT). Step 3. Select any pins to be skipped by the I/O Crossbar using the Port Skip registers (PnSKIP). Step 4. Assign Port pins to desired peripherals (XBR0, XBR1). Step 5. Enable the Crossbar (XBARE = `1'). IO N Page 129 C8051F320/1 Advanced Information Figure 14.5. XBR0: Port I/O Crossbar Register 0 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 N Bit0 CP1AE CP1E CP0AE CP0E SYSCKE SMB0E SPI0E URT0E 00000000 SFR Address: Bit7: Bit6: Bit5: Bit4: Bit3: Bit1: Bit0: AD VA NC Page 130 ED IN Bit2: CP1AE: Comparator1 Asynchronous Output Enable 0: Asynchronous CP1 unavailable at Port pin. 1: Asynchronous CP1 routed to Port pin. CP1E: Comparator1 Output Enable 0: CP1 unavailable at Port pin. 1: CP1 routed to Port pin. CP0AE: Comparator0 Asynchronous Output Enable 0: Asynchronous CP0 unavailable at Port pin. 1: Asynchronous CP0 routed to Port pin. CP0E: Comparator0 Output Enable 0: CP0 unavailable at Port pin. 1: CP0 routed to Port pin. SYSCKE: /SYSCLK Output Enable 0: /SYSCLK unavailable at Port pin. 1: /SYSCLK output routed to Port pin. SMB0E: SMBus I/O Enable 0: SMBus I/O unavailable at Port pins. 1: SMBus I/O routed to Port pins. SPI0E: SPI I/O Enable 0: SPI I/O unavailable at Port pins. 1: SPI I/O routed to Port pins. URT0E: UART I/O Output Enable 0: UART I/O unavailable at Port pin. 1: UART TX0, RX0 routed to Port pins P0.4 and P0.5. DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM AT IO 0xE1 Advanced Information C8051F320/1 Figure 14.6. XBR1: Port I/O Crossbar Register 1 R/W R/W R/W R/W R/W R/W Bit2 R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit1 N Bit0 WEAKPUD XBARE T1E T0E ECIE PCA0ME 00000000 SFR Address: Bit7: Bit6: Bit5: Bit4: Bit3: Bits2-0: (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC WEAKPUD: Port I/O Weak Pull-up Disable. 0: Weak Pull-ups enabled (except for Ports whose I/O are configured as analog input or push-pull output). 1: Weak Pull-ups disabled. XBARE: Crossbar Enable. 0: Crossbar disabled; all Port drivers disabled. 1: Crossbar enabled. T1E: T1 Enable 0: T1 unavailable at Port pin. 1: T1 routed to Port pin. T0E: T0 Enable 0: T0 unavailable at Port pin. 1: T0 routed to Port pin. ECIE: PCA0 External Counter Input Enable 0: ECI unavailable at Port pin. 1: ECI routed to Port pin. PCA0ME: PCA Module I/O Enable Bits. 000: All PCA I/O unavailable at Port pins. 001: CEX0 routed to Port pin. 010: CEX0, CEX1 routed to Port pins. 011: CEX0, CEX1, CEX2 routed to Port pins. 100: CEX0, CEX1, CEX2, CEX3 routed to Port pins. 101: CEX0, CEX1, CEX2, CEX3, CEX4 routed to Port pins. 110: Reserved. 111: Reserved. ED IN FO RM AT IO 0xE2 Page 131 C8051F320/1 14.3. General Purpose Port I/O Advanced Information AD VA NC Page 132 ED IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM AT Port pins that remain unassigned by the Crossbar and are not used by analog peripherals can be used for general purpose I/O. Ports3-0 are accessed through corresponding special function registers (SFRs) that are both byte addressable and bit addressable. When writing to a Port, the value written to the SFR is latched to maintain the output data value at each pin. When reading, the logic levels of the Port's input pins are returned regardless of the XBRn settings (i.e., even when the pin is assigned to another signal by the Crossbar, the Port register can always read its corresponding Port I/O pin). The exception to this is the execution of the read-modify-write instructions. The read-modify-write instructions when operating on a Port SFR are the following: ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ and MOV, CLR or SETB, when the destination is an individual bit in a Port SFR. For these instructions, the value of the register (not the pin) is read, modified, and written back to the SFR. IO N Advanced Information Figure 14.7. P0: Port0 Register C8051F320/1 P0.7 Bit7 P0.6 Bit6 P0.5 Bit5 P0.4 Bit4 P0.3 Bit3 P0.2 Bit2 P0.1 Bit1 N P0.0 Bit0 (bit addressable) R/W Bit0 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 11111111 SFR Address: IO 0x80 Figure 14.8. P0MDIN: Port0 Input Mode Register R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 IN FO R/W Bit3 RM R/W Bit2 AT R/W Bit1 Bits7-0: P0.[7:0] Write - Output appears on I/O pins per Crossbar Registers (when XBARE = `1'). 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P0MDOUT.n bit = 0). Read - Always reads `0' if selected as analog input in register P0MDIN. Directly reads Port pin when configured as digital input. 0: P0.n pin is logic low. 1: P0.n pin is logic high. Reset Value 11111111 SFR Address: Bits7-0: (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC Analog Input Configuration Bits for P0.7-P0.0 (respectively). Port pins configured as analog inputs have their weak pull-up, digital driver, and digital receiver disabled. 0: Corresponding P0.n pin is configured as an analog input. 1: Corresponding P0.n pin is not configured as an analog input. ED 0xF1 Page 133 C8051F320/1 Advanced Information Figure 14.9. P0MDOUT: Port0 Output Mode Register N Bit0 R/W Bit0 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Reset Value 00000000 SFR Address: IO 0xA4 Bits7-0: Figure 14.10. P0SKIP: Port0 Skip Register R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 FO R/W Bit3 RM R/W Bit2 (Note: When SDA and SCL appear on any of the Port I/O, each are open-drain regardless of the value of P0MDOUT). AT R/W Bit1 Output Configuration Bits for P0.7-P0.0 (respectively): ignored if corresponding bit in register P0MDIN is logic 0. 0: Corresponding P0.n Output is open-drain. 1: Corresponding P0.n Output is push-pull. Reset Value 00000000 SFR Address: IN 0xD4 Bits7-0: AD Page 134 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. VA NC ED P0SKIP[7:0]: Port0 Crossbar Skip Enable Bits. These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as analog inputs (for ADC or Comparator) or used as special functions (VREF input, external oscillator circuit, CNVSTR input) should be skipped by the Crossbar. 0: Corresponding P0.n pin is not skipped by the Crossbar. 1: Corresponding P0.n pin is skipped by the Crossbar. Advanced Information Figure 14.11. P1: Port1 Register C8051F320/1 P1.7 Bit7 P1.6 Bit6 P1.5 Bit5 P1.4 Bit4 P1.3 Bit3 P1.2 Bit2 P1.1 Bit1 N P1.0 Bit0 (bit addressable) R/W Bit0 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 11111111 SFR Address: IO 0x90 Figure 14.12. P1MDIN: Port1 Input Mode Register R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 IN FO R/W Bit3 RM R/W Bit2 AT R/W Bit1 Bits7-0: P1.[7:0] Write - Output appears on I/O pins per Crossbar Registers (when XBARE = `1'). 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P1MDOUT.n bit = 0). Read - Always reads `0' if selected as analog input in register P1MDIN. Directly reads Port pin when configured as digital input. 0: P1.n pin is logic low. 1: P1.n pin is logic high. Reset Value 11111111 SFR Address: Bits7-0: (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC Analog Input Configuration Bits for P1.7-P1.0 (respectively). Port pins configured as analog inputs have their weak pull-up, digital driver, and digital receiver disabled. 0: Corresponding P1.n pin is configured as an analog input. 1: Corresponding P1.n pin is not configured as an analog input. ED 0xF2 Page 135 C8051F320/1 Advanced Information Figure 14.13. P1MDOUT: Port1 Output Mode Register N Bit0 R/W Bit0 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Reset Value 00000000 SFR Address: IO 0xA5 Bits7-0: Figure 14.14. P1SKIP: Port1 Skip Register R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 FO R/W Bit3 RM R/W Bit2 AT R/W Bit1 Output Configuration Bits for P1.7-P1.0 (respectively): ignored if corresponding bit in register P1MDIN is logic 0. 0: Corresponding P1.n Output is open-drain. 1: Corresponding P1.n Output is push-pull. Reset Value 00000000 SFR Address: 0xD5 Bits7-0: AD Page 136 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. VA NC ED P1SKIP[7:0]: Port1 Crossbar Skip Enable Bits. These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as analog inputs (for ADC or Comparator) or used as special functions (VREF input, external oscillator circuit, CNVSTR input) should be skipped by the Crossbar. 0: Corresponding P1.n pin is not skipped by the Crossbar. 1: Corresponding P1.n pin is skipped by the Crossbar. IN Advanced Information Figure 14.15. P2: Port2 Register C8051F320/1 P2.7 Bit7 P2.6 Bit6 P2.5 Bit5 P2.4 Bit4 P2.3 Bit3 P2.2 Bit2 P2.1 Bit1 N P2.0 Bit0 (bit addressable) R/W Bit0 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 11111111 SFR Address: IO 0xA0 Note: P2.7-P2.4 only available on C8051F320 devices. Writes to these Ports do not require XBARE = `1'. Figure 14.16. P2MDIN: Port2 Input Mode Register R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 IN FO R/W Bit3 RM R/W Bit2 AT R/W Bit1 Bits7-0: P2.[7:0] Write - Output appears on I/O pins per Crossbar Registers (when XBARE = `1'). 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P2MDOUT.n bit = 0). Read - Always reads `0' if selected as analog input in register P2MDIN. Directly reads Port pin when configured as digital input. 0: P2.n pin is logic low. 1: P2.n pin is logic high. Reset Value 11111111 SFR Address: Bits7-0: Note: P2.7-P2.4 only available on C8051F320 devices. (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC Analog Input Configuration Bits for P2.7-P2.0 (respectively). Port pins configured as analog inputs have their weak pull-up, digital driver, and digital receiver disabled. 0: Corresponding P2.n pin is configured as an analog input. 1: Corresponding P2.n pin is not configured as an analog input. ED 0xF3 Page 137 C8051F320/1 Advanced Information Figure 14.17. P2MDOUT: Port2 Output Mode Register N Bit0 R/W Bit0 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Reset Value 00000000 SFR Address: IO 0xA6 Bits7-0: R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 FO R/W Bit3 Figure 14.18. P2SKIP: Port2 Skip Register R/W Bit2 R/W Bit1 Reset Value RM Note: P2.7-P2.4 only available on C8051F320 devices. AT Output Configuration Bits for P2.7-P2.0 (respectively): ignored if corresponding bit in register P2MDIN is logic 0. 0: Corresponding P2.n Output is open-drain. 1: Corresponding P2.n Output is push-pull. 00000000 SFR Address: IN 0xD6 Bits7-4: Bits3-0: AD Page 138 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. VA NC Unused. Read = 0000b. Write = don't care. P2SKIP[3:0]: Port2 Crossbar Skip Enable Bits. These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as analog inputs (for ADC or Comparator) or used as special functions (VREF input, external oscillator circuit, CNVSTR input) should be skipped by the Crossbar. 0: Corresponding P2.n pin is not skipped by the Crossbar. 1: Corresponding P2.n pin is skipped by the Crossbar. ED Advanced Information Figure 14.19. P3: Port3 Register C8051F320/1 P3.7 Bit7 P3.6 Bit6 P3.5 Bit5 P3.4 Bit4 P3.3 Bit3 P3.2 Bit2 P3.1 Bit1 N P3.0 Bit0 (bit addressable) R/W Bit0 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 11111111 SFR Address: IO 0xB0 Figure 14.20. P3MDIN: Port3 Input Mode Register R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 Reset Value IN FO RM AT Bits7-0: P3.[7:0] Write - Output appears on I/O pins. 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P3MDOUT.n bit = 0). Read - Always reads `0' if selected as analog input in register P3MDIN. Directly reads Port pin when configured as digital input. 0: P3.n pin is logic low. 1: P3.n pin is logic high. 00000001 SFR Address: 0xF4 (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED Bits7-1: Bit0: UNUSED. Read = 0000000b; Write = don't care. Analog Input Configuration Bit for P3.0. Port pins configured as analog inputs have their weak pull-up, digital driver, and digital receiver disabled. 0: Corresponding P3.n pin is configured as an analog input. 1: Corresponding P3.n pin is not configured as an analog input. Page 139 C8051F320/1 Advanced Information Figure 14.21. P3MDOUT: Port3 Output Mode Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 N Bit0 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 SFR Address: IO 1.0 25 0xA7 Table 14.1. Port I/O DC Electrical Characteristics VDD = 2.7 to 3.6V, -40C to +85C unless otherwise specified PARAMETERS CONDITIONS IOH = -3mA, Port I/O push-pull Output High Voltage IOH = -10A, Port I/O push-pull IOH = -10mA, Port I/O push-pull IOL = 8.5mA MIN VDD-0.7 VDD-0.1 VDD-0.8 0.6 0.1 2.0 0.8 1 40 V V V A V TYP MAX UNITS Output Low Voltage Input High Voltage Input Low Voltage Input Leakage Current AD VA NC Weak Pull-up On, VIN = 0 V Page 140 ED IOL = 10A IOL = 25mA Weak Pull-up Off IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM AT Bits7-1: Bit0: UNUSED. Read = 0000000b; Write = don't care. Output Configuration Bit for P3.0; ignored if corresponding bit in register P3MDIN is logic 0. 0: Corresponding P3.n Output is open-drain. 1: Corresponding P3.n Output is push-pull. Advanced Information 15. C8051F320/1 UNIVERSAL SERIAL BUS CONTROLLER (USB0) Endpoint0 VDD D+ Data Transfer Control DIN/OUT RM OUT OUT AT USB Control, Status, and Interrupt Registers CIP-51 Core Transceiver Serial Interface Engine (SIE) Endpoint1 Endpoint2 IN IN IN Endpoint3 OUT (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC Important Note: This document assumes a comprehensive understanding of the USB Protocol. Terms and abbreviations used in this document are defined in the USB Specification. We encourage you to review the latest version of the USB Specification before proceeding. ED IN FO USB FIFOs (1k RAM) IO Page 141 Figure 15.1. USB0 Block Diagram N C8051F320/1 devices include a complete Full/Low Speed USB function on-chip. The USB Function Controller (USB0) consists of a Serial Interface Engine (SIE), USB Transceiver (including matching resistors and configurable pull-up resistors), 1k FIFO block, and clock recovery mechanism for crystal-less operation. No external components are required. The USB Function Controller and Transceiver is Universal Serial Bus Specification 2.0 compliant. C8051F320/1 15.1. Endpoint Addressing Advanced Information A total of eight endpoint pipes are available. The control endpoint (Endpoint0) always functions as a bi-directional IN/OUT endpoint. The other endpoints are implemented as three pairs of IN/OUT endpoint pipes: Table 15.1. Endpoint Addressing Scheme Endpoint Endpoint0 Endpoint1 Endpoint2 Endpoint3 Associated Pipes Endpoint0 IN Endpoint0 OUT Endpoint1 IN Endpoint1 OUT Endpoint2 IN Endpoint2 OUT Endpoint3 IN Endpoint3 OUT 15.2. USB Transceiver Important Note: The USB clock should be active before the Transceiver is enabled. AD VA NC Page 142 ED IN The USB Transceiver is configured via the USB0XCN register shown in Figure 15.2. This configuration includes Transceiver enable/disable, pull-up resistor enable/disable, and device speed selection (Full or Low Speed). When bit SPEED = `1', USB0 operates as a Full Speed USB function, and the on-chip pull-up resistor (if enabled) appears on the D+ pin. When bit SPEED = `0', USB0 operates as a Low Speed USB function, and the on-chip pull-up resistor (if enabled) appears on the D- pin. Bits4-0 of register USB0XCN can be used for Transceiver testing as described in Figure 15.2. The pull-up resistor is enabled only when VBUS is present (see Section "8.2. VBUS Detection" on page 67 for details on VBUS detection). DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM USB Protocol Address 0x00 0x00 0x81 0x01 0x82 0x02 0x83 0x03 AT IO N Advanced Information C8051F320/1 Figure 15.2. USB0XCN: USB0 Transceiver Control R/W R/W R/W R/W Bit4 R/W Bit3 R R N R Reset Value PREN Bit7 PHYEN Bit6 SPEED Bit5 PHYTST1 PHYTST0 DFREC Bit2 Dp Bit1 Dn 00000000 SFR Address: IO Bit0 0xD7 Bit5: Bit2: Bit1: Bit0: (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD DFREC: Differential Receiver The state of this bit indicates the current differential value present on the D+ and D- lines when PHYEN = `1'. 0: Differential `0' signaling on the bus. 1: Differential `1' signaling on the bus. Dp: D+ Signal Status This bit indicates the current logic level of the D+ pin. 0: D+ signal currently at logic 0. 1: D+ signal currently at logic 1. Dn: D- Signal Status This bit indicates the current logic level of the D- pin. 0: D- signal currently at logic 0. 1: D- signal currently at logic 1. VA NC ED PHYTST[1:0] 00b 01b 10b 11b Mode Mode 0: Normal (non-test mode) Mode 1: Differential `1' Forced Mode 2: Differential `0' Forced Mode 3: Single-Ended `0' Forced IN Bits4-3: FO RM D+ X 1 0 0 Bit6: AT DX 0 1 0 Bit7: PREN: Internal Pull-up Resistor Enable The location of the pull-up resistor (D+ or D-) is determined by the SPEED bit. 0: Internal pull-up resistor disabled (device effectively detached from the USB network). 1: Internal pull-up resistor enabled when VBUS is present (device attached to the USB network). PHYEN: Physical Layer Enable This bit enables/disables the USB0 physical layer transceiver. 0: Transceiver disabled (suspend). 1: Transceiver enabled (normal). SPEED: USB0 Speed Select This bit selects the USB0 speed. 0: USB0 operates as a Low Speed device. If enabled, the internal pull-up resistor appears on the Dline. 1: USB0 operates as a Full Speed device. If enabled, the internal pull-up resistor appears on the D+ line. PHYTST1-0: Physical Layer Test These bits can be used to test the USB0 transceiver. Page 143 C8051F320/1 15.3. USB Register Access Advanced Information The USB0 controller registers listed in Table 15.2 are accessed through two SFRs: USB0 Address (USB0ADR) and USB0 Data (USB0DAT). The USB0ADR register selects which USB register is targeted by reads/writes of the USB0DAT register. See Figure 15.3. Endpoint control/status registers are accessed by first writing the USB register INDEX with the target endpoint number. Once the target endpoint number is written to the INDEX register, the control/status registers associated with the target endpoint may be accessed. See the "Indexed Registers" section of Table 15.2 for a list of endpoint control/status registers. Important Note: The USB clock must be active when accessing USB registers. Figure 15.3. USB0 Register Access Scheme 8051 SFRs RM FO IN ED USB0DAT AT USB Controller Interrupt Registers FIFO Access Common Registers Index Register Endpoint0 Control/ Status Registers Endpoint1 Control/ Status Registers Endpoint2 Control/ Status Registers Endpoint3 Control/ Status Registers AD VA NC USB0ADR Page 144 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. IO N Advanced Information C8051F320/1 Figure 15.4. USB0ADR: USB0 Indirect Address Register R/W R/W R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 N R/W Bit0 Reset Value BUSY Bit7 AUTORD Bit6 USBADDR 00000000 SFR Address: IO 0x96 Bit6: Bits5-0: (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED IN FO RM AT Bits7: BUSY: USB0 Register Read Busy Flag This bit is used during indirect USB0 register accesses. Software should write `1' to this bit to initiate a read of the USB0 register targeted by the USBADDR bits (USB0ADR.[5-0]). The target address and BUSY bit may be written in the same write to USB0ADR. After BUSY is set to `1', hardware will clear BUSY when the targeted register data is ready in the USB0DAT register. Software should check BUSY for `0' before writing to USB0DAT. Write: 0: No effect. 1: A USB0 indirect register read is initiated at the address specified by the USBADDR bits. Read: 0: USB0DAT register data is valid. 1: USB0 is busy accessing an indirect register; USB0DAT register data is invalid. AUTORD: USB0 Register Auto-read Flag This bit is used for block FIFO reads. 0: BUSY must be written manually for each USB0 indirect register read. 1: The next indirect register read will automatically be initiated when software reads USB0DAT (USBADDR bits will not be changed). USBADDR: USB0 Indirect Register Address These bits hold a 6-bit address used to indirectly access the USB0 core registers. Table 15.2 lists the USB0 core registers and their indirect addresses. Reads and writes to USB0DAT will target the register indicated by the USBADDR bits. Page 145 C8051F320/1 Advanced Information Figure 15.5. USB0DAT: USB0 Data Register R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Reset Value USB0DAT N Bit0 R/W Bit0 00000000 SFR Address: IO R/W Bit1 0x97 This SFR is used to indirectly read and write USB0 registers. R R R ED R Figure 15.6. INDEX: USB0 Endpoint Index (USB Register) R/W Bit3 R/W Reset Value Bit7 Bit6 Bit5 IN - Read Procedure: 1. Poll for BUSY (USB0ADR.7) => `0'. 2. Load the target USB0 register address into the USBADDR bits in register USB0ADR. 3. Write `1' to the BUSY bit in register USB0ADR (steps 2 and 3 can be performed in the same write). 4. Poll for BUSY (USB0ADR.7) => `0'. 5. Read data from USB0DAT. 6. Repeat from Step 2 (Step 2 may be skipped when reading the same USB0 register; Step 3 may be skipped when the AUTORD bit (USB0ADR.6) is logic 1). FO RM Bit2 Write Procedure: 1. Poll for BUSY (USB0ADR.7) => `0'. 2. Load the target USB0 register address into the USBADDR bits in register USB0ADR. 3. Write data to USB0DAT. 4. Repeat (Step 2 may be skipped when writing to the same USB0 register). EPSEL AT 00000000 USB Address: VA NC Bit4 0x0E Bits7-4: Bits3-0: Unused. Read = 0000b; Write = don't care. EPSEL: Endpoint Select These bits select which endpoint is targeted when indexed USB0 registers are accessed. INDEX 0x0 0x1 0x2 0x3 0x4 - 0xF Target Endpoint 0 1 2 3 Reserved AD Page 146 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. Advanced Information USB Register Name IN1INT OUT1INT CMINT IN1IE OUT1IE CMIE FADDR POWER FRAMEL FRAMEH INDEX CLKREC FIFOn E0CSR EINCSRL EINCSRH EOUTCSRL EOUTCSRH E0CNT EOUTCNTL EOUTCNTH USB Register Address 0x02 0x04 0x06 0x07 0x09 0x0B 0x00 0x01 0x0C 0x0D 0x0E 0x0F 0x20-0x23 0x11 0x12 0x14 0x15 0x16 0x17 C8051F320/1 Table 15.2. USB0 Controller Registers Description Interrupt Registers Endpoint0 and Endpoints1-3 IN Interrupt Flags Endpoints1-3 OUT Interrupt Flags Common USB Interrupt Flags Endpoint0 and Endpoints1-3 IN Interrupt Enables Endpoints1-3 OUT Interrupt Enables Common USB Interrupt Enables Common Registers Function Address Power Management Frame Number Low Byte Frame Number High Byte Endpoint Index Selection Clock Recovery Control Endpoints0-3 FIFOs Indexed Registers Endpoint0 Control / Status Endpoint IN Control / Status High Byte Endpoint IN Control / Status Low Byte Endpoint OUT Control / Status High Byte Endpoint OUT Control / Status Low Byte Number of Received Bytes in Endpoint0 FIFO Endpoint OUT Packet Count Low Byte Endpoint OUT Packet Count High Byte Page Number 155 156 157 158 158 159 151 153 154 154 146 148 150 162 166 167 169 170 163 170 170 (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED IN FO RM AT IO N Page 147 C8051F320/1 15.4. USB Clock Configuration Advanced Information Clock Recovery circuitry uses the incoming USB data stream to adjust the internal oscillator; this allows the internal oscillator (and 4x Clock Multiplier) to meet the requirements for USB clock tolerance. Clock Recovery should be used in the following configurations: Communication Speed Full Speed Low Speed USB Clock 4x Clock Multiplier Internal Oscillator / 2 4x Clock Multiplier Input Internal Oscillator N/A When operating USB0 as a Low Speed function with Clock Recovery, software must write `1' to the CRLOW bit to enable Low Speed Clock Recovery. Clock Recovery is typically not necessary in Low Speed mode. Single Step Mode can be used to help the Clock Recovery circuitry to lock when high noise levels are present on the USB network. This mode is not required (or recommended) in typical USB environments. Figure 15.7. CLKREC: Clock Recovery Control (USB Register) R/W R/W R/W R/W Bit4 IN FO R/W Bit3 RM R/W AT R/W Bit1 IO N R/W Bit0 USB0 is capable of communication as a Full or Low Speed USB function. Communication speed is selected via the SPEED bit in SFR USB0XCN. When operating as a Low Speed function, the USB0 clock must be 6 MHz. When operating as a Full Speed function, the USB0 clock must be 48 MHz. Clock options are described in Section "13. Oscillators" on page 115. The USB0 clock is selected via SFR CLKSEL (see Figure 13.6 on Page 123). Reset Value CRE Bit7 CRSSEN Bit6 CRLOW Bit5 Reserved Bit2 00001001 USB Address: 0x0F Bit7: Bit6: Bit5: AD Bits4-0: CRE: Clock Recovery Enable. This bit enables/disables the USB clock recovery feature. 0: Clock recovery disabled. 1: Clock recovery enabled. CRSSEN: Clock Recovery Single Step. This bit forces the oscillator calibration into `single-step' mode during clock recovery. 0: Normal calibration mode. 1: Single step mode. CRLOW: Low Speed Clock Recovery Mode. This bit must be set to `1' if clock recovery is used when operating as a Low Speed USB device. 0: Full Speed Mode. 1: Low Speed Mode. Reserved. Read = Variable. Must Write = 1001b. VA NC Page 148 ED DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. Advanced Information 15.5. FIFO Management C8051F320/1 1024 bytes of on-chip XRAM are used as FIFO space for USB0. This FIFO space is split between Endpoints0-3 as shown in Figure 15.8. FIFO space allocated for Endpoints1-3 is configurable as IN, OUT, or both (Split Mode: half IN, half OUT). Figure 15.8. USB FIFO Allocation 0x07FF Endpoint0 (64 bytes) 0x07C0 0x07BF Endpoint1 (128 bytes) 0x0740 0x073F Endpoint2 (256 bytes) 0x0640 0x063F Free (64 bytes) 0x0400 ED 0x03FF User XRAM (1024 bytes) 15.5.1. FIFO Split Mode The FIFO space for Endpoints1-3 can be split such that the upper half of the FIFO space is used by the IN endpoint, and the lower half is used by the OUT endpoint. For example: if the Endpoint3 FIFO is configured for Split Mode, the upper 256 bytes (0x0540 to 0x063F) are used by Endpoint3 IN and the lower 256 bytes (0x0440 to 0x053F) are used by Endpoint3 OUT. 15.5.2. FIFO Double Buffering FIFO slots for Endpoints1-3 can be configured for double-buffered mode. In this mode, the maximum packet size is halved and the FIFO may contain two packets at a time. This mode is available for Endpoints1-3. When an endpoint is configured for Split Mode, double buffering may be enabled for the IN Endpoint and/or the OUT end- (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD If an endpoint FIFO is not configured for Split Mode, that endpoint IN/OUT pair's FIFOs are combined to form a single IN or OUT FIFO. In this case only one direction of the endpoint IN/OUT pair may be used at a time. The endpoint direction (IN/OUT) is determined by the DIRSEL bit in the corresponding endpoint's EINCSRH register (see Figure 15.23). VA NC 0x0000 IN 0x0440 0x043F FO USB Clock Domain System Clock Domain Endpoint3 (512 bytes) RM AT Configurable as IN, OUT, or both (Split Mode) IO Page 149 N C8051F320/1 Advanced Information point. When Split Mode is not enabled, double-buffering may be enabled for the entire endpoint FIFO. See Table 15.3 for a list of maximum packet sizes for each FIFO configuration. Table 15.3. FIFO Configurations Endpoint Number 0 1 2 3 Split Mode Enabled? N/A N Y N Y N Y Maximum IN Packet Size (Double Buffer Disabled / Enabled) Maximum OUT Packet Size (Double Buffer Disabled / Enabled) 64 128 / 64 64 / 32 256 / 128 128 / 64 512 / 256 256 / 128 64 / 32 128 / 64 256 / 128 15.5.3. FIFO Access Figure 15.9. FIFOn: USB0 Endpoint FIFO Access (USB Registers) R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value IN FIFODATA FO Each endpoint FIFO is accessed through a corresponding FIFOn register. A read of an endpoint FIFOn register unloads one byte from the FIFO; a write of an endpoint FIFOn register loads one byte into the endpoint FIFO. When an endpoint FIFO is configured for Split Mode, a read of the endpoint FIFOn register unloads one byte from the OUT endpoint FIFO; a write of the endpoint FIFOn register loads one byte into the IN endpoint FIFO. RM AT IO N ED 00000000 USB Address: 0x20 - 0x23 IN/OUT Endpoint FIFO 0 1 2 3 VA NC USB Addresses 0x20 - 0x23 provide access to the 4 pairs of endpoint FIFOs: USB Address 0x20 0x21 0x22 0x23 AD Page 150 Writing to the FIFO address loads data into the IN FIFO for the corresponding endpoint. Reading from the FIFO address unloads data from the OUT FIFO for the corresponding endpoint. DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. Advanced Information 15.6. Function Addressing C8051F320/1 Figure 15.10. FADDR: USB0 Function Address (USB Register) R R/W Bit6 R/W Bit5 R/W Bit4 R/W R/W Bit2 AT R/W Bit1 IO The FADDR register holds the current USB0 function address. Software should write the host-assigned 7-bit function address to the FADDR register when received as part of a SET_ADDRESS command. A new address written to FADDR will not take effect (USB0 will not respond to the new address) until the end of the current transfer (typically following the status phase of the SET_ADDRESS command transfer). The UPDATE bit (FADDR.7) is set to `1' by hardware when software writes a new address to the FADDR register. Hardware clears the UPDATE bit when the new address takes effect as described above. N R/W Bit0 Reset Value Update Bit7 Function Address Bit3 00000000 USB Address: Bit7: Bits6-0: (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED IN Update: Function Address Update Set to `1' when software writes the FADDR register. USB0 clears this bit to `0' when the new address takes effect. 0: The last address written to FADDR is in effect. 1: The last address written to FADDR is not yet in effect. Function Address Holds the 7-bit function address for USB0. This address should be written by software when the SET_ADDRESS standard device request is received on Endpoint0. The new address takes effect when the device request completes. FO RM 0x00 Page 151 C8051F320/1 15.7. Advanced Information Function Configuration and Control The USB register POWER (Figure 15.11) is used to configure and control USB0 at the device level (enable/disable, Reset/Suspend/Resume handling, etc.). USB Reset: The USBRST bit (POWER.3) is set to `1' by hardware when Reset signaling is detected on the bus. Upon this detection, the following occur: 1. 2. 3. 4. 5. 6. The USB0 Address is reset (FADDR = 0x00). Endpoint FIFOs are flushed. Control/status registers are reset to 0x00 (E0CSR, EINCSRL, EINCSRH, EOUTCSRL, EOUTCSRH). USB register INDEX is reset to 0x00. All USB interrupts (excluding the Suspend interrupt) are enabled and their corresponding flags cleared. A USB Reset interrupt is generated if enabled. Writing a `1' to the USBRST bit will generate an asynchronous USB0 reset. All USB registers are reset to their default values following this asynchronous reset. Suspend Mode: With Suspend Detection enabled (SUSEN = `1'), USB0 will enter Suspend Mode when Suspend signaling is detected on the bus. An interrupt will be generated if enabled (SUSINTE = `1'). The Suspend Interrupt Service Routine (ISR) should perform application-specific configuration tasks such as disabling appropriate peripherals and/or configuring clock sources for low power modes. See Section "13. Oscillators" on page 115 for more details on internal oscillator configuration, including the Suspend mode feature of the internal oscillator. USB Enable: USB0 is disabled following a Power-On-Reset (POR). USB0 is enabled by clearing the USBINH bit (POWER.4). Once written to `0', the USBINH can only be set to `1' by one of the following: (1) a Power-On-Reset (POR), or (2) an asynchronous USB0 reset generated by writing `1' to the USBRST bit (POWER.3). Software should perform all USB0 configuration before enabling USB0. The configuration sequence should be performed as follows: Step 1. Step 2. Step 3. Step 4. Step 5. Select and enable the USB clock source. Reset USB0 by writing USBRST= `1'. Configure and enable the USB Transceiver. Perform any USB0 function configuration (interrupts, Suspend detect). Enable USB0 by writing USBINH = `0'. AD VA NC ISO Update: When software writes `1' to the ISOUP bit (POWER.7), the ISO Update function is enabled. With ISO Update enabled, new packets written to an ISO IN endpoint will not be transmitted until a new Start-Of-Frame (SOF) is received. If the ISO IN endpoint receives an IN token before a SOF, USB0 will transmit a zero-length packet. When ISOUP = `1', ISO Update is enabled for all ISO endpoints. Page 152 ED Resume Signaling: USB0 will exit Suspend mode if Resume signaling is detected on the bus. A Resume interrupt will be generated upon detection if enabled (RESINTE = `1'). Software may force a Remote Wakeup by writing `1' to the RESUME bit (POWER.2). When forcing a Remote Wakeup, software should write RESUME = `0' to end Resume signaling 10-15 ms after the Remote Wakeup is initiated (RESUME = `1'). IN USB0 exits Suspend mode when any of the following occur: (1) Resume signaling is detected or generated, (2) Reset signaling is detected, or (3) a device or USB reset occurs. If suspended, the internal oscillator will exit Suspend mode upon any of the above listed events. DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM AT IO N Advanced Information C8051F320/1 Figure 15.11. POWER: USB0 Power (USB Register) R/W R/W R/W R/W R/W R/W R N R/W Bit0 Reset Value ISOUD Bit7 Bit6 Bit5 USBINH Bit4 USBRST Bit3 RESUME Bit2 SUSMD Bit1 SUSEN 00010000 USB Address: IO 0x01 Bits6-5: Bit4: Bit2: Bit1: (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD Bit0: VA NC ED IN Bit3: FO RM AT Bit7: ISOUD: ISO Update This bit affects all IN Isochronous endpoints. 0: When software writes INPRDY = `1', USB0 will send the packet when the next IN token is received. 1: When software writes INPRDY = `1', USB0 will wait for a SOF token before sending the packet. If an IN token is received before a SOF token, USB0 will send a zero-length data packet. Unused. Read = 00b. Write = don't care. USBINH: USB0 Inhibit This bit is set to `1' following a power-on reset (POR) or an asynchronous USB0 reset (see Bit3: RESET). Software should clear this bit after all USB0 and transceiver initialization is complete. Software cannot set this bit to `1'. 0: USB0 enabled. 1: USB0 inhibited. All USB traffic is ignored. USBRST: Reset Detect Writing `1' to this bit forces an asynchronous USB0 reset. Reading this bit provides bus reset status information. Read: 0: Reset signaling is not present on the bus. 1: Reset signaling detected on the bus. RESUME: Force Resume Software can force resume signaling on the bus to wake USB0 from suspend mode. Writing a `1' to this bit while in Suspend mode (SUSMD = `1') forces USB0 to generate Resume signaling on the bus (a remote Wakeup event). Software should write RESUME = `0' after 10 ms to15 ms to end the Resume signaling. An interrupt is generated, and hardware clears SUSMD, when software writes RESUME = `0'. SUSMD: Suspend Mode Set to `1' by hardware when USB0 enters suspend mode. Cleared by hardware when software writes RESUME = `0' (following a remote wakeup) or reads the CMINT register after detection of Resume signaling on the bus. 0: USB0 not in suspend mode. 1: USB0 in suspend mode. SUSEN: Suspend Detection Enable 0: Suspend detection disabled. USB0 will ignore suspend signaling on the bus. 1: Suspend detection enabled. USB0 will enter suspend mode if it detects suspend signaling on the bus. Page 153 C8051F320/1 Advanced Information Figure 15.12. FRAMEL: USB0 Frame Number Low (USB Register) R Bit7 R Bit6 R Bit5 R Bit4 R Bit3 R Bit2 R Bit1 R Reset Value Frame Number Low N Bit0 R Bit0 00000000 USB Address: IO R Bit1 0x0C Bits7-0: Figure 15.13. FRAMEH: USB0 Frame Number High (USB Register) R R R R R RM R Bit2 AT Frame Number Low This register contains bits7-0 of the last received frame number. Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Frame Number High 00000000 USB Address: 0x0D Bits7-3: Bits2-0: Unused. Read = 0. Write = don't care. Frame Number High Byte This register contains bits10-8 of the last received frame number. AD Page 154 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. VA NC ED IN FO Advanced Information 15.8. Interrupts C8051F320/1 Important Note: Reading a USB interrupt flag register resets all flags in that register to `0'. Figure 15.14. IN1INT: USB0 IN Endpoint Interrupt (USB Register) R R R R R R AT R IO N R The read-only USB0 interrupt flags are located in the USB registers shown in Figure 15.14 through Figure 15.16. The associated interrupt enable bits are located in the USB registers shown in Figure 15.17 through Figure 15.19. A USB0 interrupt is generated when any of the USB interrupt flags is set to `1'. The USB0 interrupt is enabled via the EIE1 SFR (see Section "9.3. Interrupt Handler" on page 85). Reset Value Bit7 Bit6 Bit5 Bit4 IN3 Bit3 IN2 Bit2 IN1 Bit1 EP0 Bit0 00000000 USB Address: Bits7-4: Bit3: Bit2: Bit1: Bit0: (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC Unused. Read = 0000b. Write = don't care. IN3: IN Endpoint 3 Interrupt-pending Flag This bit is cleared when software reads the IN1INT register. 0: IN Endpoint 3 interrupt inactive. 1: IN Endpoint 3 interrupt active. IN2: IN Endpoint 2 Interrupt-pending Flag This bit is cleared when software reads the IN1INT register. 0: IN Endpoint 2 interrupt inactive. 1: IN Endpoint 2 interrupt active. IN1: IN Endpoint 1 Interrupt-pending Flag This bit is cleared when software reads the IN1INT register. 0: IN Endpoint 1 interrupt inactive. 1: IN Endpoint 1 interrupt active. EP0: Endpoint 0 Interrupt-pending Flag This bit is cleared when software reads the IN1INT register. 0: Endpoint 0 interrupt inactive. 1: Endpoint 0 interrupt active. ED IN FO RM 0x02 Page 155 C8051F320/1 Advanced Information Figure 15.15. OUT1INT: USB0 Out Endpoint Interrupt (USB Register) R R R R R R R N R Reset Value Bit7 Bit6 Bit5 Bit4 OUT3 Bit3 OUT2 Bit2 OUT1 Bit1 - 00000000 USB Address: IO Bit0 0x04 Bit2: Bit1: Bit0: AD VA NC Page 156 ED DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. IN FO RM AT Bits7-4: Bit3: Unused. Read = 0000b. Write = don't care. OUT3: OUT Endpoint 3 Interrupt-pending Flag This bit is cleared when software reads the OUT1INT register. 0: OUT Endpoint 3 interrupt inactive. 1: OUT Endpoint 3 interrupt active. OUT2: OUT Endpoint 2 Interrupt-pending Flag This bit is cleared when software reads the OUT1INT register. 0: OUT Endpoint 2 interrupt inactive. 1: OUT Endpoint 2 interrupt active. OUT1: OUT Endpoint 1 Interrupt-pending Flag This bit is cleared when software reads the OUT1INT register. 0: OUT Endpoint 1 interrupt inactive. 1: OUT Endpoint 1 interrupt active. Unused. Read = 0; Write = don't care. Advanced Information C8051F320/1 Figure 15.16. CMINT: USB0 Common Interrupt (USB Register) R R R R R R R R Reset Value Bit7 Bit6 Bit5 Bit4 SOF Bit3 RSTINT Bit2 RSUINT Bit1 N Bit0 SUSINT 00000000 USB Address: IO 0x06 Bit2: Bit1: Bit0: (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED IN FO RM AT Bits7-4: Bit3: Unused. Read = 0000b; Write = don't care. SOF: Start of Frame Interrupt Set by hardware when a SOF token is received. This interrupt event is synthesized by hardware: an interrupt will be generated when hardware expects to receive a SOF event, even if the actual SOF signal is missed or corrupted. This bit is cleared when software reads the CMINT register. 0: SOF interrupt inactive. 1: SOF interrupt active. RSTINT: Reset Interrupt-pending Flag Set by hardware when Reset signaling is detected on the bus. This bit is cleared when software reads the CMINT register. 0: Reset interrupt inactive. 1: Reset interrupt active. RSUINT: Resume Interrupt-pending Flag Set by hardware when Resume signaling is detected on the bus while USB0 is in suspend mode. This bit is cleared when software reads the CMINT register. 0: Resume interrupt inactive. 1: Resume interrupt active. SUSINT: Suspend Interrupt-pending Flag When Suspend detection is enabled (bit SUSEN in register POWER), this bit is set by hardware when Suspend signaling is detected on the bus. This bit is cleared when software reads the CMINT register. 0: Suspend interrupt inactive. 1: Suspend interrupt active. Page 157 C8051F320/1 Advanced Information Figure 15.17. IN1IE: USB0 IN Endpoint Interrupt Enable (USB Register) R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 IN3E Bit3 IN2E Bit2 IN1E Bit1 N EP0E Bit0 R/W 00001111 USB Address: IO R/W Bit3 0x07 Bit2: Bit1: Figure 15.18. OUT1IE: USB0 Out Endpoint Interrupt Enable (USB Register) R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 ED - - - IN - FO OUT3E OUT2E Bit2 Bit0: RM OUT1E Bit1 AT Bit0 Bits7-4: Bit3: Unused. Read = 0000b. Write = don't care. IN3E: IN Endpoint 3 Interrupt Enable 0: IN Endpoint 3 interrupt disabled. 1: IN Endpoint 3 interrupt enabled. IN2E: IN Endpoint 2 Interrupt Enable 0: IN Endpoint 2 interrupt disabled. 1: IN Endpoint 2 interrupt enabled. IN1E: IN Endpoint 1 Interrupt Enable 0: IN Endpoint 1 interrupt disabled. 1: IN Endpoint 1 interrupt enabled. EP0E: Endpoint 0 Interrupt Enable 0: Endpoint 0 interrupt disabled. 1: Endpoint 0 interrupt enabled. 00001110 USB Address: Bit4 0x09 Bit2: Bit1: Bit0: AD VA NC Bits7-4: Bit3: Unused. Read = 0000b. Write = don't care. OUT3E: OUT Endpoint 3 Interrupt Enable 0: OUT Endpoint 3 interrupt disabled. 1: OUT Endpoint 3 interrupt enabled. OUT2E: OUT Endpoint 2 Interrupt Enable 0: OUT Endpoint 2 interrupt disabled. 1: OUT Endpoint 2 interrupt enabled. OUT1E: OUT Endpoint 1 Interrupt Enable 0: OUT Endpoint 1 interrupt disabled. 1: OUT Endpoint 1 interrupt enabled. Unused. Read = 0; Write = don't' care. Page 158 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. Advanced Information C8051F320/1 Figure 15.19. CMIE: USB0 Common Interrupt Enable (USB Register) R/W R/W R/W R/W R/W R/W Bit2 R/W Bit1 R/W Reset Value USB Address: Bit7 Bit6 Bit5 Bit4 SOFE Bit3 RSTINTE RSUINTE SUSINTE 00000110 Bit0 IO RM AT N 0x0B Bits7-4: Bit3: Bit2: Bit1: 15.9. The Serial Interface Engine 15.10. Endpoint0 Endpoint0 is managed through the USB register E0CSR (Figure 15.20). The INDEX register must be loaded with 0x00 to access the E0CSR register. An Endpoint0 interrupt is generated when: The E0CNT register (Figure 15.21) holds the number of received data bytes in the Endpoint0 FIFO. (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD 2. 3. 4. 5. 1. A data packet (OUT or SETUP) has been received and loaded into the Endpoint0 FIFO. The OPRDY bit (E0CSR.0) is set to `1' by hardware. An IN data packet has successfully been unloaded from the Endpoint0 FIFO and transmitted to the host; INPRDY is reset to `0' by hardware. An IN transaction is completed (this interrupt generated during the status phase of the transaction). Hardware sets the STSTL bit (E0CSR.2) after a control transaction ended due to a protocol violation. Hardware sets the SUEND bit (E0CSR.4) because a control transfer ended before firmware sets the DATAEND bit (E0CSR.3). VA NC The SIE will not interrupt the processor when corrupted/erroneous packets are received. ED The Serial Interface Engine (SIE) performs all low level USB protocol tasks, interrupting the processor when data has successfully been transmitted or received. When receiving data, the SIE will interrupt the processor when a complete data packet has been received; appropriate handshaking signals are automatically generated by the SIE. When transmitting data, the SIE will interrupt the processor when a complete data packet has been transmitted and the appropriate handshake signal has been received. IN FO Bit0: Unused. Read = 0000b; Write = don't care. SOFE: Start of Frame Interrupt Enable 0: SOF interrupt disabled. 1: SOF interrupt enabled. RSTINTE: Reset Interrupt Enable 0: Reset interrupt disabled. 1: Reset interrupt enabled. RSUINTE: Resume Interrupt Enable 0: Resume interrupt disabled. 1: Resume interrupt enabled. SUSINTE: Suspend Interrupt Enable 0: Suspend interrupt disabled. 1: Suspend interrupt enabled. Page 159 C8051F320/1 Advanced Information Hardware will automatically detect protocol errors and send a STALL condition in response. Firmware may force a STALL condition to abort the current transfer. When a STALL condition is generated, the STSTL bit will be set to `1' and an interrupt generated. The following conditions will cause hardware to generate a STALL condition: 1. The host sends an OUT token during a OUT data phase after the DATAEND bit has been set to `1'. 2. The host sends an IN token during an IN data phase after the DATAEND bit has been set to `1'. 3. The host sends a packet that exceeds the maximum packet size for Endpoint0. 4. The host sends a non-zero length DATA1 packet during the status phase of an IN transaction. Firmware sets the SDSTL bit (E0CSR.5) to `1'. 15.10.2.Endpoint0 IN Transactions When a SETUP request is received that requires USB0 to transmit data to the host, one or more IN requests will be sent by the host. For the first IN transaction, firmware should load an IN packet into the Endpoint0 FIFO, and set the INPRDY bit (E0CSR.1). An interrupt will be generated when an IN packet is transmitted successfully. Note that no interrupt will be generated if an IN request is received before firmware has loaded a packet into the Endpoint0 FIFO. If the requested data exceeds the maximum packet size for Endpoint0 (as reported to the host), the data should be split into multiple packets; each packet should be of the maximum packet size excluding the last (residual) packet. If the requested data is an integer multiple of the maximum packet size for Endpoint0, the last data packet should be a zero-length packet signaling the end of the transfer. Firmware should set the DATAEND bit to `1' after loading into the Endpoint0 FIFO the last data packet for a transfer. Upon reception of the first IN token for a particular control transfer, Endpoint0 is said to be in Transmit Mode. In this mode, only IN tokens should be sent by the host to Endpoint0. The SUEND bit (E0CSR.4) is set to `1' if a SETUP or OUT token is received while Endpoint0 is in Transmit Mode. Endpoint0 will remain in Transmit Mode until any of the following occur: 1. 2. 3. USB0 receives an Endpoint0 SETUP or OUT token. Firmware sends a packet less than the maximum Endpoint0 packet size. Firmware sends a zero-length packet. Firmware should set the DATAEND bit (E0CSR.3) to `1' when performing (2) and (3) above. AD The SIE will transmit a NAK in response to an IN token if there is no packet ready in the IN FIFO (INPRDY = `0'). VA NC Page 160 ED IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM All control transfers must begin with a SETUP packet. SETUP packets are similar to OUT packets, containing an 8-byte data field sent by the host. Any SETUP packet containing a command field of anything other than 8 bytes will be automatically rejected by USB0. An Endpoint0 interrupt is generated when the data from a SETUP packet is loaded into the Endpoint0 FIFO. Software should unload the command from the Endpoint0 FIFO, decode the command, perform any necessary tasks, and set the SOPRDY bit to indicate that it has serviced the OUT packet. AT 15.10.1.Endpoint0 SETUP Transactions IO N Advanced Information 15.10.3.Endpoint0 OUT Transactions C8051F320/1 Upon reception of the first OUT token for a particular control transfer, Endpoint0 is said to be in Receive Mode. In this mode, only OUT tokens should be sent by the host to Endpoint0. The SUEND bit (E0CSR.4) is set to `1' if a SETUP or IN token is received while Endpoint0 is in Receive Mode. Endpoint0 will remain in Receive mode until: 1. 2. 3. The SIE receives a SETUP or IN token. The host sends a packet less than the maximum Endpoint0 packet size. The host sends a zero-length packet. Firmware should set the DATAEND bit (E0CSR.3) to `1' when the expected amount of data has been received. The SIE will transmit a STALL condition if the host sends an OUT packet after the DATAEND bit has been set by firmware. An interrupt will be generated with the STSTL bit (E0CSR.2) set to `1' after the STALL is transmitted. (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED IN FO RM AT IO If the amount of data required for the transfer exceeds the maximum packet size for Endpoint0, the data will be split into multiple packets. If the requested data is an integer multiple of the maximum packet size for Endpoint0 (as reported to the host), the host will send a zero-length data packet signaling the end of the transfer. N When a SETUP request is received that requires the host to transmit data to USB0, one or more OUT requests will be sent by the host. When an OUT packet is successfully received by USB0, hardware will set the OPRDY bit (E0CSR.0) to `1' and generate an Endpoint0 interrupt. Following this interrupt, firmware should unload the OUT packet from the Endpoint0 FIFO and set the SOPRDY bit (E0CSR.6) to `1'. Page 161 C8051F320/1 Advanced Information Figure 15.20. E0CSR: USB0 Endpoint0 Control (USB Register) R/W R/W R/W R R/W R/W R/W N R Bit0 Reset Value SSUEND Bit7 SOPRDY Bit6 SDSTL Bit5 SUEND Bit4 DATAEND Bit3 STSTL Bit2 INPRDY Bit1 OPRDY 00000000 USB Address: IO 0x11 Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: AD VA NC Page 162 ED IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM Bit6: AT Bit7: SSUEND: Serviced Setup End Write: Software should set this bit to `1' after servicing a Setup End (bit SUEND) event. Hardware clears the SUEND bit when software writes `1' to SSUEND. Read: This bit always reads `0'. SOPRDY: Serviced OPRDY Write: Software should write `1' to this bit after servicing a received Endpoint0 packet. The OPRDY bit will be cleared by a write of `1' to SOPRDY. Read: This bit always reads `0'. SDSTL: Send Stall Software can write `1' to this bit to terminate the current transfer (due to an error condition, unexpected transfer request, etc.). Hardware will clear this bit to `0' when the STALL handshake is transmitted. SUEND: Setup End Hardware sets this read-only bit to `1' when a control transaction ends before software has written `1' to the DATAEND bit. Hardware clears this bit when software writes `1' to SSUEND. DATAEND: Data End Software should write `1' to this bit: 1. When writing `1' to INPRDY for the last outgoing data packet. 2. When writing `1' to INPRDY for a zero-length data packet. 3. When writing `1' to SOPRDY after servicing the last incoming data packet. This bit is automatically cleared by hardware. STSTL: Sent Stall Hardware sets this bit to `1' after transmitting a STALL handshake signal. This flag must be cleared by software. INPRDY: IN Packet Ready Software should write `1' to this bit after loading a data packet into the Endpoint0 FIFO for transmit. Hardware clears this bit and generates an interrupt under either of the following conditions: 1. The packet is transmitted. 2. The packet is overwritten by an incoming SETUP packet. 3. The packet is overwritten by an incoming OUT packet. OPRDY: OUT Packet Ready Hardware sets this read-only bit and generates an interrupt when a data packet has been received. This bit is cleared only when software writes `1' to the SOPRDY bit. Advanced Information C8051F320/1 Figure 15.21. E0CNT: USB0 Endpoint 0 Data Count (USB Register) R R Bit6 R Bit5 R Bit4 R R Bit2 R Bit1 R Reset Value Bit7 E0CNT Bit3 N Bit0 00000000 USB Address: IO 0x16 (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED IN FO RM AT Bit7: Bits6-0: Unused. Read = 0; Write = don't care. E0CNT: Endpoint 0 Data Count This 7-bit number indicates the number of received data bytes in the Endpoint 0 FIFO. This number is only valid while bit OPRDY is a `1'. Page 163 C8051F320/1 15.11. Configuring Endpoints1-3 Advanced Information Endpoints1-3 can be configured as IN, OUT, or both IN/OUT (Split Mode) as described in Section 15.5.1. The endpoint mode (Split/Normal) is selected via the SPLIT bit in register EINCSRH. When SPLIT = `0', the corresponding endpoint functions as either IN or OUT; the endpoint direction is selected by the DIRSEL bit in register EINCSRH. 15.12. Controlling Endpoints1-3 IN Endpoints1-3 IN are managed via USB registers EINCSRL and EINCSRH. All IN endpoints can be used for Interrupt, Bulk, or Isochronous transfers. Isochronous (ISO) mode is enabled by writing `1' to the ISO bit in register EINCSRH. Bulk and Interrupt transfers are handled identically by hardware. An Endpoint1-3 IN interrupt is generated by any of the following conditions: 1. 2. 3. An IN packet is successfully transferred to the host. Software writes `1' to the FLUSH bit (EINCSRL.3) when the target FIFO is not empty. Hardware generates a STALL condition. 15.12.1.Endpoints1-3 IN Interrupt or Bulk Mode When the ISO bit (EINCSRH.6) = `0' the target endpoint operates in Bulk or Interrupt Mode. Once an endpoint has been configured to operate in Bulk/Interrupt IN mode (typically following an Endpoint0 SET_INTERFACE command), firmware should load an IN packet into the endpoint IN FIFO and set the INPRDY bit (EINCSRL.0). Upon reception of an IN token, hardware will transmit the data, clear the INPRDY bit, and generate an interrupt. Writing `1' to INPRDY without writing any data to the endpoint FIFO will cause a zero-length packet to be transmitted upon reception of the next IN token. A Bulk or Interrupt pipe can be shut down (or Halted) by writing `1' to the SDSTL bit (EINCSRL.4). While SDSTL = `1', hardware will respond to all IN requests with a STALL condition. Each time hardware generates a STALL condition, an interrupt will be generated and the STSTL bit (EINCSRL.5) set to `1'. The STSTL bit must be reset to `0' by firmware. When firmware writes `1' to the FCDT bit (EINCSRH.3), the data toggle for each IN packet will be toggled continuously, regardless of the handshake received from the host. This feature is typically used by Interrupt endpoints functioning as rate feedback communication for Isochronous endpoints. When FCDT = `0', the data toggle bit will only be toggled when an ACK is sent from the host in response to an IN packet. AD Hardware will automatically reset INPRDY to `0' when a packet slot is open in the endpoint FIFO. Note that if double buffering is enabled for the target endpoint, it is possible for firmware to load two packets into the IN FIFO at a time. In this case, hardware will reset INPRDY to `0' immediately after firmware loads the first packet into the FIFO and sets INPRDY to `1'. An interrupt will not be generated in this case; an interrupt will only be generated when a data packet is transmitted. VA NC Page 164 ED IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM AT When SPLIT = `1', the corresponding endpoint FIFO is split, and both IN and OUT pipes are available. IO N Endpoints1-3 are configured and controlled through their own sets of the following control/status registers: IN registers EINCSRL and EINCSRH, and OUT registers EOUTCSRL and EOUTCSRH. Only one set of endpoint control/status registers is mapped into the USB register address space at a time, defined by the contents of the INDEX register (Figure 15.6). Advanced Information 15.12.2.Endpoints1-3 IN Isochronous Mode C8051F320/1 If there is not a data packet ready in the endpoint FIFO when USB0 receives an IN token from the host, USB0 will transmit a zero-length data packet and set the UNDRUN bit (EINCSRL.2) to `1'. The ISO Update feature (see Section 15.7) can be useful in starting a double buffered ISO IN endpoint. If the host has already set up the ISO IN pipe (has begun transmitting IN tokens) when firmware writes the first data packet to the endpoint FIFO, the next IN token may arrive and the first data packet sent before firmware has written the second (double buffered) data packet to the FIFO. The ISO Update feature ensures that any data packet written to the endpoint FIFO will not be transmitted during the current frame; the packet will only be sent after a SOF signal has been received. (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED IN FO RM AT Hardware will automatically reset INPRDY (EINCSRL.0) to `0' when a packet slot is open in the endpoint FIFO. Note that if double buffering is enabled for the target endpoint, it is possible for firmware to load two packets into the IN FIFO at a time. In this case, hardware will reset INPRDY to `0' immediately after firmware loads the first packet into the FIFO and sets INPRDY to `1'. An interrupt will not be generated in this case; an interrupt will only be generated when a data packet is transmitted. IO N When the ISO bit (EINCSRH.6) is set to `1', the target endpoint operates in Isochronous (ISO) mode. Once an endpoint has been configured for ISO IN mode, the host will send one IN token (data request) per frame; the location of data within each frame may vary. Because of this, it is recommended that double buffering be enabled for ISO IN endpoints. Page 165 C8051F320/1 Advanced Information Figure 15.22. EINCSRL: USB0 IN Endpoint Control High Byte (USB Register) R W R/W R/W W R/W R/W N R/W Bit0 Reset Value Bit7 CLRDT Bit6 STSTL Bit5 SDSTL Bit4 FLUSH Bit3 UNDRUN Bit2 FIFONE Bit1 INPRDY 00000000 USB Address: IO 0x11 Bit4: Bit3: Bit2: Bit1: Bit0: AD VA NC Page 166 ED IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM Bit5: AT Bit7: Bit6: Unused. Read = 0; Write = don't care. CLRDT: Clear Data Toggle. Write: Software should write `1' to this bit to reset the IN Endpoint data toggle to `0'. Read: This bit always reads `0'. STSTL: Sent Stall Hardware sets this bit to `1' when a STALL handshake signal is transmitted. The FIFO is flushed, and the INPRDY bit cleared. This flag must be cleared by software. SDSTL: Send Stall. Software should write `1' to this bit to generate a STALL handshake in response to an IN token. Software should write `0' to this bit to terminate the STALL signal. This bit has no effect in ISO mode. FLUSH: FIFO Flush. Writing a `1' to this bit flushes the next packet to be transmitted from the IN Endpoint FIFO. The FIFO pointer is reset and the INPRDY bit is cleared. If the FIFO contains multiple packets, software must write `1' to FLUSH for each packet. Hardware resets the FLUSH bit to `0' when the FIFO flush is complete. UNDRUN: Data Underrun. The function of this bit depends on the IN Endpoint mode: ISO: Set when a zero-length packet is sent after an IN token is received while bit INPRDY = `0'. Interrupt/Bulk: Set when a NAK is returned in response to an IN token. This bit must be cleared by software. FIFONE: FIFO Not Empty. 0: The IN Endpoint FIFO is empty. 1. The IN Endpoint FIFO contains one or more packets. INPRDY: In Packet Ready. Software should write `1' to this bit after loading a data packet into the IN Endpoint FIFO. Hardware clears INPRDY due to any of the following: 1. A data packet is transmitted. 2. Double buffering is enabled (DBIEN = `1') and there is an open FIFO packet slot. 3. If the endpoint is in Isochronous Mode (ISO = `1') and ISOUD = `1', INPRDY will read `0' until the next SOF is received. An interrupt (if enabled) will be generated when hardware clears INPRDY as a result of a packet being transmitted. Advanced Information C8051F320/1 Figure 15.23. EINCSRH: USB0 IN Endpoint Control Low Byte (USB Register) R/W R/W R/W R R/W R/W R R Reset Value DBIEN Bit7 ISO Bit6 DIRSEL Bit5 Bit4 FCDT Bit3 SPLIT Bit2 Bit1 N Bit0 00000000 USB Address: IO 0x12 Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED Bits1-0: DBIEN: IN Endpoint Double-buffer Enable. 0: Double-buffering disabled for the selected IN endpoint. 1: Double-buffering enabled for the selected IN endpoint. ISO: Isochronous Transfer Enable. This bit enables/disables isochronous transfers on the current endpoint. 0: Endpoint configured for bulk/interrupt transfers. 1: Endpoint configured for isochronous transfers. DIRSEL: Endpoint Direction Select. This bit is valid only when the selected FIFO is not split (SPLIT = `0'). 0: Endpoint direction selected as OUT. 1: Endpoint direction selected as IN. Unused. Read = `0'. Write = don't care. FCDT: Force Data Toggle. 0: Endpoint data toggle switches only when an ACK is received following a data packet transmission. 1: Endpoint data toggle forced to switch after every data packet is transmitted, regardless of ACK reception. SPLIT: FIFO Split Enable. When SPLIT = `1', the selected endpoint FIFO is split. The upper half of the selected FIFO is used by the IN endpoint; the lower half of the selected FIFO is used by the OUT endpoint. Unused. Read = 00b; Write = don't care. IN FO RM AT Page 167 C8051F320/1 Advanced Information 15.13. Controlling Endpoints1-3 OUT Endpoints1-3 OUT are managed via USB registers EOUTCSRL and EOUTCSRH. All OUT endpoints can be used for Interrupt, Bulk, or Isochronous transfers. Isochronous (ISO) mode is enabled by writing `1' to the ISO bit in register EOUTCSRH. Bulk and Interrupt transfers are handled identically by hardware. An Endpoint1-3 OUT interrupt may be generated by the following: 1. 2. Hardware sets the OPRDY bit (EINCSRL.0) to `1'. Hardware generates a STALL condition. 15.13.1.Endpoints1-3 OUT Interrupt or Bulk Mode A Bulk or Interrupt pipe can be shut down (or Halted) by writing `1' to the SDSTL bit (EOUTCSRL.5). While SDSTL = `1', hardware will respond to all OUT requests with a STALL condition. Each time hardware generates a STALL condition, an interrupt will be generated and the STSTL bit (EOUTCSRL.6) set to `1'. The STSTL bit must be reset to `0' by firmware. Hardware will automatically set OPRDY when a packet is ready in the OUT FIFO. Note that if double buffering is enabled for the target endpoint, it is possible for two packets to be ready in the OUT FIFO at a time. In this case, hardware will set OPRDY to `1' immediately after firmware unloads the first packet and resets OPRDY to `0'. A second interrupt will be generated in this case. 15.13.2.Endpoints1-3 OUT Isochronous Mode Each time a data packet is received, hardware will load the received data packet into the endpoint FIFO, set the OPRDY bit (EOUTCSRL.0) to `1', and generate an interrupt (if enabled). Firmware would typically use this interrupt to unload the data packet from the endpoint FIFO and reset the OPRDY bit to `0'. If a data packet is received when there is no room in the endpoint FIFO, an interrupt will be generated and the OVRUN bit (EOUTCSRL.2) set to `1'. If USB0 receives an ISO data packet with a CRC error, the data packet will be loaded into the endpoint FIFO, OPRDY will be set to `1', an interrupt (if enabled) will be generated, and the DATAERR bit (EOUTCSRL.3) will be set to `1'. Software should check the DATAERR bit each time a data packet is unloaded from an ISO OUT endpoint FIFO. AD VA NC When the ISO bit (EOUTCSRH.6) is set to `1', the target endpoint operates in Isochronous (ISO) mode. Once an endpoint has been configured for ISO OUT mode, the host will send exactly one data per USB frame; the location of the data packet within each frame may vary, however. Because of this, it is recommended that double buffering be enabled for ISO OUT endpoints. Page 168 ED IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM When the ISO bit (EOUTCSRH.6) = `0' the target endpoint operates in Bulk or Interrupt mode. Once an endpoint has been configured to operate in Bulk/Interrupt OUT mode (typically following an Endpoint0 SET_INTERFACE command), hardware will set the OPRDY bit (EOUTCSRL.0) to `1' and generate an interrupt upon reception of an OUT token and data packet. The number of bytes in the current OUT data packet (the packet ready to be unloaded from the FIFO) is given in the EOUTCNTH and EOUTCNTL registers. In response to this interrupt, firmware should unload the data packet from the OUT FIFO and reset the OPRDY bit to `0'. AT IO N Advanced Information C8051F320/1 Figure 15.24. EOUTCSRL: USB0 OUT Endpoint Control High Byte (USB Register) W R/W R/W W R R/W R N R/W Bit0 Reset Value CLRDT Bit7 STSTL Bit6 SDSTL Bit5 FLUSH Bit4 DATERR Bit3 OVRUN Bit2 FIFOFUL Bit1 OPRDY 00000000 USB Address: IO 0x14 Bit6: Bit5: Bit4: Bit2: Bit1: Bit0: (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED IN Bit3: FO RM AT Bit7: CLRDT: Clear Data Toggle Write: Software should write `1' to this bit to reset the OUT endpoint data toggle to `0'. Read: This bit always reads `0'. STSTL: Sent Stall Hardware sets this bit to `1' when a STALL handshake signal is transmitted. This flag must be cleared by software. SDSTL: Send Stall Software should write `1' to this bit to generate a STALL handshake. Software should write `0' to this bit to terminate the STALL signal. This bit has no effect in ISO mode. FLUSH: FIFO Flush Writing a `1' to this bit flushes the next packet to be read from the OUT endpoint FIFO. The FIFO pointer is reset and the OPRDY bit is cleared. If the FIFO contains multiple packets, software must write `1' to FLUSH for each packet. Hardware resets the FLUSH bit to `0' when the FIFO flush is complete. DATERR: Data Error In ISO mode, this bit is set by hardware if a received packet has a CRC or bit-stuffing error. It is cleared when software clears OPRDY. This bit is only valid in ISO mode. OVRUN: Data Overrun This bit is set by hardware when an incoming data packet cannot be loaded into the OUT endpoint FIFO. This bit is only valid in ISO mode, and must be cleared by software. 0: No data overrun. 1: A data packet was lost because of a full FIFO since this flag was last cleared. FIFOFUL: OUT FIFO Full This bit indicates the contents of the OUT FIFO. If double buffering is enabled for the endpoint (DBIEN = `1'), the FIFO is full when the FIFO contains two packets. If DBIEN = `0', the FIFO is full when the FIFO contains one packet. 0: OUT endpoint FIFO is not full. 1: OUT endpoint FIFO is full. OPRDY: OUT Packet Ready Hardware sets this bit to `1' and generates an interrupt when a data packet is available. Software should clear this bit after each data packet is unloaded from the OUT endpoint FIFO. Page 169 C8051F320/1 Advanced Information Figure 15.25. EOUTCSRH: USB0 OUT Endpoint Control Low Byte (USB Register) R/W R/W R/W R/W R R R R Reset Value DBOEN Bit7 ISO Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 N Bit0 R Bit0 R 00000000 USB Address: IO R R 0x15 Bit7: Bit6: Bits5-0: R Bit7 R Bit6 R Bit5 R Bit4 FO R Figure 15.26. EOUTCNTL: USB0 OUT Endpoint Count Low (USB Register) R Bit2 Reset Value IN EOCL RM DBOEN: Double-buffer Enable 0: Double-buffering disabled for the selected OUT endpoint. 1: Double-buffering enabled for the selected OUT endpoint. ISO: Isochronous Transfer Enable This bit enables/disables isochronous transfers on the current endpoint. 0: Endpoint configured for bulk/interrupt transfers. 1: Endpoint configured for isochronous transfers. Unused. Read = 000000b; Write = don't care. AT 00000000 Bit1 USB Address: Bit3 0x16 Bits7-0: Figure 15.27. EOUTCNTH: USB0 OUT Endpoint Count High (USB Register) R R R R R R Reset Value Bit7 VA NC - ED Bit4 EOCL: OUT Endpoint Count Low Byte EOCL holds the lower 8-bits of the 10-bit number of data bytes in the last received packet in the current OUT endpoint FIFO. This number is only valid while OPRDY = `1'. Bit3 Bit2 Bit1 E0CH Bit0 00000000 USB Address: Bit6 Bit5 0x17 AD Bits7-2: Bits1-0: Unused. Read = 00000. Write = don't care. EOCH: OUT Endpoint Count High Byte EOCH holds the upper 2-bits of the 10-bit number of data bytes in the last received packet in the current OUT endpoint FIFO. This number is only valid while OPRDY = `1'. Page 170 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. Advanced Information C8051F320/1 Table 15.4. USB Transceiver Electrical Characteristics VDD = 3.0 to 3.6V, -40C to +85C unless otherwise specified PARAMETERS SYMBOL CONDITIONS MIN TRANSMITTER VOH 2.8 Output High Voltage VOL Output Low Voltage VCRS Output Crossover Point 1.3 Driving High ZDRV Output High Impedance Driving Low Full Speed (D+ Pull-up) RPU Pull-up Resistance Low Speed (D- Pull-up) Low Speed 75 TR Output Rise Time Full Speed 4 Low Speed 75 TF Output Fall Time Full Speed 4 RECEIVER VIH TBD Input High Voltage VIL Input Low Voltage Differential Input VDI | (D+) - (D-) | 0.2 Sensitivity Differential Input ComVCM 0.8 mon Mode Range IL Input Leakage Current Note: Refer to the USB Specification for timing diagrams and symbol definitions. N TYP MAX UNITS V V V k IO 38 38 1.5 TBD 0.8 2.0 RM AT 300 20 300 20 ns ns FO 0.8 V V V IN 2.5 V A (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED Page 171 C8051F320/1 Advanced Information Notes AD VA NC Page 172 ED IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM AT IO N Advanced Information 16. SYSTEM MANAGEMENT BUS (SMBUS0) C8051F320/1 Figure 16.1. SMBus Block Diagram SMB0CN MT SSAAAS AXTTCRC I SMAOKBK TO RL ED QO RE S T SMB0CF E I BESSSS N N U XMMMM SHSTBBBB M YHTFCC B OOT S S LEE10 D IN ED SMBUS CONTROL LOGIC FO 00 01 10 11 T0 Overflow T1 Overflow TMR2H Overflow TMR2L Overflow SCL FILTER SCL Control SDA Control N C R O S S B A R SDA VA NC Interrupt Request Arbitration SCL Synchronization SCL Generation (Master Mode) SDA Control Data Path IRQ Generation Control RM FILTER AT N The SMBus interface may operate as a master and/or slave, and may function on a bus with multiple masters. The SMBus provides control of SDA (serial data), SCL (serial clock) generation and synchronization, arbitration logic, and START/STOP control and generation. Three SFRs are associated with the SMBus: SMB0CF configures the SMBus; SMB0CN controls the status of the SMBus; and SMB0DAT is the data register, used for both transmitting and receiving SMBus data and slave addresses. IO The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specification, version 1.1, and compatible with the I2C serial bus. Reads and writes to the interface by the system controller are byte oriented with the SMBus interface autonomously controlling the serial transfer of the data. Data can be transferred at up to 1/10th of the system clock as a master or slave (this can be faster than allowed by the SMBus specification, depending on the system clock used). A method of extending the clock-low duration is available to accommodate devices with different speed capabilities on the same bus. N Port I/O SMB0DAT 76543210 (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD Page 173 C8051F320/1 16.1. Supporting Documents Advanced Information It is assumed the reader is familiar with or has access to the following supporting documents: 1. 2. 3. The I2C-Bus and How to Use It (including specifications), Philips Semiconductor. The I2C-Bus Specification -- Version 2.0, Philips Semiconductor. System Management Bus Specification -- Version 1.1, SBS Implementers Forum. 16.2. SMBus Configuration Figure 16.2. Typical SMBus Configuration VDD = 5V VDD = 3V IN FO VDD = 5V RM Figure 16.2 shows a typical SMBus configuration. The SMBus specification allows any recessive voltage between 3.0 V and 5.0 V; different devices on the bus may operate at different voltage levels. The bi-directional SCL (serial clock) and SDA (serial data) lines must be connected to a positive power supply voltage through a pull-up resistor or similar circuit. Every device connected to the bus must have an open-drain or open-collector output for both the SCL and SDA lines, so that both are pulled high (recessive state) when the bus is free. The maximum number of devices on the bus is limited only by the requirement that the rise and fall times on the bus not exceed 300 ns and 1000 ns, respectively. VA NC ED Master Device Slave Device 1 AT VDD = 3V Slave Device 2 IO N SDA SCL AD Page 174 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. Advanced Information 16.3. SMBus Operation C8051F320/1 The direction bit (R/W) occupies the least-significant bit position of the address byte. The direction bit is set to logic 1 to indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation. All transactions are initiated by a master, with one or more addressed slave devices as the target. The master generates the START condition and then transmits the slave address and direction bit. If the transaction is a WRITE operation from the master to the slave, the master transmits the data a byte at a time waiting for an ACK from the slave at the end of each byte. For READ operations, the slave transmits the data waiting for an ACK from the master at the end of each byte. At the end of the data transfer, the master generates a STOP condition to terminate the transaction and free the bus. Figure 16.3 illustrates a typical SMBus transaction. Figure 16.3. SMBus Transaction SCL SDA SLA6 ED SLA5-0 IN R/W FO ACK RM D7 START VA NC Slave Address + R/W AT D6-0 Data Byte A typical SMBus transaction consists of a START condition followed by an address byte (Bits7-1: 7-bit slave address; Bit0: R/W direction bit), one or more bytes of data, and a STOP condition. Each byte that is received (by a master or slave) must be acknowledged (ACK) with a low SDA during a high SCL (see Figure 16.3). If the receiving device does not ACK, the transmitting device will read a NACK (not acknowledge), which is a high SDA during a high SCL. IO Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver (WRITE), and data transfers from an addressed slave transmitter to a master receiver (READ). The master device initiates both types of data transfers and provides the serial clock pulses on SCL. The SMBus interface may operate as a master or a slave, and multiple master devices on the same bus are supported. If two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme is employed with a single master always winning the arbitration. Note that it is not necessary to specify one device as the Master in a system; any device who transmits a START and a slave address becomes the master for the duration of that transfer. N NACK STOP 16.3.1. Arbitration (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD A master may start a transfer only if the bus is free. The bus is free after a STOP condition or after the SCL and SDA lines remain high for a specified time (see Section "16.3.4. SCL High (SMBus Free) Timeout" on page 176). In the event that two or more devices attempt to begin a transfer at the same time, an arbitration scheme is employed to force one master to give up the bus. The master devices continue transmitting until one attempts a HIGH while the other transmits a LOW. Since the bus is open-drain, the bus will be pulled LOW. The master attempting the HIGH will detect a LOW SDA and lose the arbitration. The winning master continues its transmission without interruption; the losing master becomes a slave and receives the rest of the transfer if addressed. This arbitration scheme is nondestructive: one device always wins, and no data is lost. Page 175 C8051F320/1 16.3.2. Clock Low Extension Advanced Information 16.3.3. SCL Low Timeout 16.3.4. SCL High (SMBus Free) Timeout AD VA NC Page 176 ED IN The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 s, the bus is designated as free. When the SMBFTE bit in SMB0CF is set, the bus will be considered free if SCL and SDA remain high for more than 10 SMBus clock source periods. If the SMBus is waiting to generate a Master START, the START will be generated following this timeout. Note that a clock source is required for free timeout detection, even in a slaveonly implementation. DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM When the SMBTOE bit in SMB0CF is set, Timer 3 is used to detect SCL low timeouts. Timer 3 is forced to reload when SCL is high, and allowed to count when SCL is low. With Timer 3 enabled and configured to overflow after 25 ms (and SMBTOE set), the Timer 3 interrupt service routine can be used to reset (disable and re-enable) the SMBus in the event of an SCL low timeout. Timer 3 configuration details can be found in Section "19.3. Timer 3" on page 228. AT If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore, the master cannot force the SCL line high to correct the error condition. To solve this problem, the SMBus protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than 25 ms as a "timeout" condition. Devices that have detected the timeout condition must reset the communication no later than 10 ms after detecting the timeout condition. IO N SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line LOW to extend the clock low period, effectively decreasing the serial clock frequency. Advanced Information 16.4. Using the SMBus C8051F320/1 The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting control for serial transfers; higher level protocol is determined by user software. The SMBus interface provides the following application-independent features: * * * * * * * Byte-wise serial data transfers Clock signal generation on SCL (Master Mode only) and SDA data synchronization Timeout/bus error recognition, as defined by the SMB0CF configuration register START/STOP timing, detection, and generation Bus arbitration Interrupt generation Status information These options are selected in the SMB0CF register, as described in Section "16.4.1. SMBus Configuration Register" on page 178. (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED * * * * Timeout detection (SCL Low Timeout and/or Bus Free Timeout) SDA setup and hold time extensions Slave event enable/disable Clock source selection IN SMBus configuration options include: FO Interrupts are also generated to indicate the beginning of a transfer when a master (START generated), or the end of a transfer when a slave (STOP detected). Software should read the SMB0CN (SMBus Control register) to find the cause of the SMBus interrupt. The SMB0CN register is described in Section "16.4.2. SMB0CN Control Register" on page 181; Table 16.4 provides a quick SMB0CN decoding reference. RM SMBus interrupts are generated for each data byte or slave address that is transferred. When transmitting, this interrupt is generated after the ACK cycle so that software may read the received ACK value; when receiving data, this interrupt is generated before the ACK cycle so that software may define the outgoing ACK value. See Section "16.5. SMBus Transfer Modes" on page 185 for more details on transmission sequences. AT IO Page 177 N C8051F320/1 16.4.1. SMBus Configuration Register Advanced Information Table 16.1. SMBus Clock Source Selection SMBCS1 SMBCS0 SMBus Clock Source 0 0 Timer 0 Overflow 0 1 Timer 1 Overflow 1 0 Timer 2 High Byte Overflow 1 1 Timer 2 Low Byte Overflow Equation 16.1. Minimum SCL High and Low Times 1 T HighMin = T LowMin = --------------------------------------------f ClockSourceOverflow Figure 16.4 shows the typical SCL generation described by Equation 16.2. Notice that THIGH is typically twice as large as TLOW. The actual SCL output may vary due to other devices on the bus (SCL may be extended low by slower slave devices, or driven low by contending master devices). The bit rate when operating as a master will never exceed the limits defined by equation Equation 16.1. AD Timer Source Overflows SCL VA NC Equation 16.2. Typical SMBus Bit Rate f ClockSourceOverflow BitRate = --------------------------------------------3 Figure 16.4. Typical SMBus SCL Generation TLow ED The selected clock source should be configured to establish the minimum SCL High and Low times as per Equation 16.1. When the interface is operating as a master (and SCL is not driven or extended by any other devices on the bus), the typical SMBus bit rate is approximated by Equation 16.2. IN FO The SMBCS1-0 bits select the SMBus clock source, which is used only when operating as a master or when the Free Timeout detection is enabled. When operating as a master, overflows from the selected source determine the absolute minimum SCL low and high times as defined in Equation 16.1. Note that the selected clock source may be shared by other peripherals so long as the timer is left running at all times. For example, Timer 1 overflows may generate the SMBus and UART baud rates simultaneously. Timer configuration is covered in Section "19. Timers" on page 215. THigh Page 178 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. RM AT SCL High Timeout IO The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes, select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is set, the SMBus is enabled for all master and slave events. Slave events may be disabled by setting the INH bit. With slave events inhibited, the SMBus interface will still monitor the SCL and SDA pins; however, the interface will NACK all received addresses and will not generate any slave interrupts. When the INH bit is set, all slave events will be inhibited following the next START (interrupts will continue for the duration of the current transfer). N Advanced Information C8051F320/1 Table 16.2. Minimum SDA Setup and Hold Times EXTHOLD 0 1 OR 1 system clock + s/w 11 system clocks delay Setup Time for ACK bit transmissions and the MSB of all data transfers. The s/w delay occurs between the time SMB0DAT or ACK is written and when SI is cleared. Note that if SI is cleared in the same write that defines the outgoing ACK value, s/w delay is zero. (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED SMBus Free Timeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see Figure 16.4). When a Free Timeout is detected, the interface will respond as if a STOP was detected (an interrupt will be generated, and STO will be set). IN FO With the SMBTOE bit set, Timer 3 should be configured to overflow after 25 ms in order to detect SCL low timeouts (see Section "16.3.3. SCL Low Timeout" on page 176). The SMBus interface will force Timer 3 to reload while SCL is high, and allow Timer 3 to count when SCL is low. The Timer 3 interrupt service routine should be used to reset SMBus communication by disabling and re-enabling the SMBus. Timer 3 configuration is described in Section "19.3. Timer 3" on page 228. RM AT Minimum SDA Setup Time Tlow - 4 system clocks Minimum SDA Hold Time 3 system clocks 12 system clocks IO N Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA setup time defines the absolute minimum time that SDA is stable before SCL transitions from low-to-high. The minimum SDA hold time defines the absolute minimum time that the current SDA value remains stable after SCL transitions from high-to-low. EXTHOLD should be set so that the minimum setup and hold times meet the SMBus Specification requirements of 250 ns and 300 ns, respectively. Table 16.2 shows the minimum setup and hold times for the two EXTHOLD settings. Setup and hold time extensions are typically necessary when SYSCLK is above 10 MHz. Page 179 C8051F320/1 Advanced Information Figure 16.5. SMB0CF: SMBus Clock/Configuration Register ENSMB Bit7 INH Bit6 BUSY Bit5 EXTHOLD SMBTOE Bit4 Bit3 SMBFTE Bit2 SMBCS1 Bit1 N Bit0 R/W R/W R R/W R/W R/W R/W R/W Reset Value SMBCS0 00000000 SFR Address: IO 0xC1 Bit7: Bit4: Bit3: Bit2: Bits1-0: AD SMBCS1 0 0 1 1 VA NC SMBCS0 0 1 0 1 Page 180 ED SMBus Clock Source Timer 0 Overflow Timer 1 Overflow Timer 2 High Byte Overflow Timer 2 Low Byte Overflow IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO Bit5: RM Bit6: ENSMB: SMBus Enable. This bit enables/disables the SMBus interface. When enabled, the interface constantly monitors the SDA and SCL pins. 0: SMBus interface disabled. 1: SMBus interface enabled. INH: SMBus Slave Inhibit. When this bit is set to logic 1, the SMBus does not generate an interrupt when slave events occur. This effectively removes the SMBus slave from the bus. Master Mode interrupts are not affected. 0: SMBus Slave Mode enabled. 1: SMBus Slave Mode inhibited. BUSY: SMBus Busy Indicator. This bit is set to logic 1 by hardware when a transfer is in progress. It is cleared to logic 0 when a STOP or free-timeout is sensed. EXTHOLD: SMBus Setup and Hold Time Extension Enable. This bit controls the SDA setup and hold times according to Table 16.2. 0: SDA Extended Setup and Hold Times disabled. 1: SDA Extended Setup and Hold Times enabled. SMBTOE: SMBus SCL Timeout Detection Enable. This bit enables SCL low timeout detection. If set to logic 1, the SMBus forces Timer 3 to reload while SCL is high and allows Timer 3 to count when SCL goes low. Timer 3 should be programmed to generate interrupts at 25 ms, and the Timer 3 interrupt service routine should reset SMBus communication. SMBFTE: SMBus Free Timeout Detection Enable. When this bit is set to logic 1, the bus will be considered free if SCL and SDA remain high for more than 10 SMBus clock source periods. SMBCS1-SMBCS0: SMBus Clock Source Selection. These two bits select the SMBus clock source, which is used to generate the SMBus bit rate. The selected device should be configured according to Equation 16.1. AT Advanced Information 16.4.2. SMB0CN Control Register C8051F320/1 SMB0CN is used to control the interface and to provide status information (see Figure 16.6). The higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to jump to service routines. MASTER and TXMODE indicate the master/slave state and transmit/receive modes, respectively. STA and STO indicate that a START and/or STOP has been detected or generated since the last SMBus interrupt. STA and STO are also used to generate START and STOP conditions when operating as a master. Writing a `1' to STA will cause the SMBus interface to enter Master Mode and generate a START when the bus becomes free (STA is not cleared by hardware after the START is generated). Writing a `1' to STO while in Master Mode will cause the interface to generate a STOP and end the current transfer after the next ACK cycle. If STO and STA are both set (while in Master Mode), a STOP followed by a START will be generated. As a receiver, writing the ACK bit defines the outgoing ACK value; as a transmitter, reading the ACK bit indicates the value received on the last ACK cycle. ACKRQ is set each time a byte is received, indicating that an outgoing ACK value is needed. When ACKRQ is set, software should write the desired outgoing value to the ACK bit before clearing SI. A NACK will be generated if software does not write the ACK bit before clearing SI. SDA will reflect the defined ACK value immediately following a write to the ACK bit; however SCL will remain low until SI is cleared. If a received slave address is not acknowledged, further slave events will be ignored until the next START is detected. The ARBLOST bit indicates that the interface has lost an arbitration. This may occur anytime the interface is transmitting (master or slave). A lost arbitration while operating as a slave indicates a bus error condition. ARBLOST is cleared by hardware each time SI is cleared. The SI bit (SMBus Interrupt Flag) is set at the beginning and end of each transfer, after each byte frame, or when an arbitration is lost; see Table 16.3 for more details. Important Note About the SI Bit: The SMBus interface is stalled while SI is set; thus SCL is held low, and the bus is stalled until software clears SI. Table 16.3 lists all sources for hardware changes to the SMB0CN bits. Refer to Table 16.4 for SMBus status decoding using the SMB0CN register. (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED IN FO RM AT IO N Page 181 C8051F320/1 Advanced Information Figure 16.6. SMB0CN: SMBus Control Register R Bit7 R Bit6 R/W R/W R Bit3 R Bit2 R/W R/W Reset Value Bit5 Bit4 Bit1 N Bit0 MASTER TXMODE STA STO ACKRQ ARBLOST ACK SI 00000000 SFR Address: Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: MASTER: SMBus Master/Slave Indicator. This read-only bit indicates when the SMBus is operating as a master. 0: SMBus operating in Slave Mode. 1: SMBus operating in Master Mode. TXMODE: SMBus Transmit Mode Indicator. This read-only bit indicates when the SMBus is operating as a transmitter. 0: SMBus in Receiver Mode. 1: SMBus in Transmitter Mode. STA: SMBus Start Flag. Write: 0: No Start generated. 1: When operating as a master, a START condition is transmitted if the bus is free (If the bus is not free, the START is transmitted after a STOP is received or a timeout is detected). If STA is set by software as an active Master, a repeated START will be generated after the next ACK cycle. Read: 0: No Start or repeated Start detected. 1: Start or repeated Start detected. STO: SMBus Stop Flag. Write: 0: No STOP condition is transmitted. 1: Setting STO to logic 1 causes a STOP condition to be transmitted after the next ACK cycle. When the STOP condition is generated, hardware clears STO to logic 0. If both STA and STO are set, a STOP condition is transmitted followed by a START condition. Read: 0: No Stop condition detected. 1: Stop condition detected (if in Slave Mode) or pending (if in Master Mode). ACKRQ: SMBus Acknowledge Request This read-only bit is set to logic 1 when the SMBus has received a byte and needs the ACK bit to be written with the correct ACK response value. ARBLOST: SMBus Arbitration Lost Indicator. This read-only bit is set to logic 1 when the SMBus loses arbitration while operating as a transmitter. A lost arbitration while a slave indicates a bus error condition. ACK: SMBus Acknowledge Flag. This bit defines the out-going ACK level and records incoming ACK levels. It should be written each time a byte is received (when ACKRQ=1), or read after each byte is transmitted. 0: A "not acknowledge" has been received (if in Transmitter Mode) OR will be transmitted (if in Receiver Mode). 1: An "acknowledge" has been received (if in Transmitter Mode) OR will be transmitted (if in Receiver Mode). SI: SMBus Interrupt Flag. This bit is set by hardware under the conditions listed in Table 16.3. SI must be cleared by software. While SI is set, SCL is held low and the SMBus is stalled. AD VA NC Page 182 ED IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM AT IO (bit addressable) 0xC0 Advanced Information C8051F320/1 Table 16.3. Sources for Hardware Changes to SMB0CN Bit MASTER TXMODE STA STO ACKRQ ARBLOST ACK SI (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED IN FO RM AT IO N Set by Hardware When: * A START is generated. Cleared by Hardware When: * A STOP is generated. * Arbitration is lost. * START is generated. * A START is detected. * SMB0DAT is written before the start of an SMBus * Arbitration is lost. frame. * SMB0DAT is not written before the start of an SMBus frame. * A START followed by an address byte is received. * Must be cleared by software. * A STOP is detected while addressed as a slave. * A pending STOP is generated. * Arbitration is lost due to a detected STOP. * A byte has been received and an ACK response * After each ACK cycle. value is needed. * A repeated START is detected as a MASTER when * Each time SI is cleared. STA is low (unwanted repeated START). * SCL is sensed low while attempting to generate a STOP or repeated START condition. * SDA is sensed low while transmitting a `1' (excluding ACK bits). * The incoming ACK value is low (ACKNOWL* The incoming ACK value is high (NOT EDGE). ACKNOWLEDGE). * A START has been generated. * Must be cleared by software. * Lost arbitration. * A byte has been transmitted and an ACK/NACK received. * A byte has been received. * A START or repeated START followed by a slave address + R/W has been received. * A STOP has been received. Page 183 C8051F320/1 16.4.3. Data Register Advanced Information Figure 16.7. SMB0DAT: SMBus Data Register R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 AT Data in SMB0DAT is always shifted out MSB first. After a byte has been received, the first bit of received data is located at the MSB of SMB0DAT. While data is being shifted out, data on the bus is simultaneously being shifted in. SMB0DAT always contains the last data byte present on the bus. In the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data or address in SMB0DAT. IO N R/W Bit0 The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software may safely read or write to the data register when the SI flag is set. Software should not attempt to access the SMB0DAT register when the SMBus is enabled and the SI flag is cleared to logic 0, as the interface may be in the process of shifting a byte of data into or out of the register. Reset Value RM 00000000 SFR Address: 0xC2 AD Page 184 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. VA NC ED IN FO Bits7-0: SMB0DAT: SMBus Data. The SMB0DAT register contains a byte of data to be transmitted on the SMBus serial interface or a byte that has just been received on the SMBus serial interface. The CPU can read from or write to this register whenever the SI serial interrupt flag (SMB0CN.0) is set to logic 1. The serial data in the register remains stable as long as the SI flag is set. When the SI flag is not set, the system may be in the process of shifting data in/out and the CPU should not attempt to access this register. Advanced Information 16.5. SMBus Transfer Modes C8051F320/1 16.5.1. Master Transmitter Mode S SLA W A Data Byte FO A Figure 16.8. Typical Master Transmitter Sequence Data Byte A P Interrupt IN Interrupt RM Interrupt Serial data is transmitted on SDA while the serial clock is output on SCL. The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the data direction bit. In this case the data direction bit (R/W) will be logic 0 (WRITE). The master then transmits one or more bytes of serial data. After each byte is transmitted, an acknowledge bit is generated by the slave. The transfer is ended when the STO bit is set and a STOP is generated. Note that the interface will switch to Master Receiver Mode if SMB0DAT is not written following a Master Transmitter interrupt. Figure 16.8 shows a typical Master Transmitter sequence. Two transmit data bytes are shown, though any number of bytes may be transmitted. Notice that the `data byte transferred' interrupts occur after the ACK cycle in this mode. Received by SMBus Interface Transmitted by SMBus Interface (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED S = START P = STOP A = ACK W = WRITE SLA = Slave Address AT IO Interrupt The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or Slave Receiver. The SMBus interface enters Master Mode any time a START is generated, and remains in Master Mode until it loses an arbitration or generates a STOP. An SMBus interrupt is generated at the end of all SMBus byte frames; however, note that the interrupt is generated before the ACK cycle when operating as a receiver, and after the ACK cycle when operating as a transmitter. N Page 185 C8051F320/1 16.5.2. Master Receiver Mode Advanced Information Figure 16.9. Typical Master Receiver Sequence S SLA R A Data Byte A Data Byte N P Interrupt Interrupt FO Interrupt RM Transmitted by SMBus Interface AD VA NC Page 186 ED IN Received by SMBus Interface S = START P = STOP A = ACK N = NACK R = READ SLA = Slave Address DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. AT Serial data is received on SDA while the serial clock is output on SCL. The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the data direction bit. In this case the data direction bit (R/W) will be logic 1 (READ). Serial data is then received from the slave on SDA while the SMBus outputs the serial clock. The slave transmits one or more bytes of serial data. After each byte is received, ACKRQ is set to `1' and an interrupt is generated. Software must write the ACK bit (SMB0CN.1) to define the outgoing acknowledge value (Note: writing a `1' to the ACK bit generates an ACK; writing a `0' generates a NACK). Software should write a `0' to the ACK bit after the last byte is received, to transmit a NACK. The interface exits Master Receiver Mode after the STO bit is set and a STOP is generated. Note that the interface will switch to Master Transmitter Mode if SMB0DAT is written while an active Master Receiver. Figure 16.9 shows a typical Master Receiver sequence. Two received data bytes are shown, though any number of bytes may be received. Notice that the `data byte transferred' interrupts occur before the ACK cycle in this mode. IO Interrupt N Advanced Information 16.5.3. Slave Receiver Mode C8051F320/1 Figure 16.10. Typical Slave Receiver Sequence RM S SLA W A Data Byte A Data Byte AT A Interrupt Serial data is received on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode when a START followed by a slave address and direction bit (WRITE in this case) is received. Upon entering Slave Receiver Mode, an interrupt is generated and the ACKRQ bit is set. Software responds to the received slave address with an ACK, or ignores the received slave address with a NACK. If the received slave address is ignored, slave interrupts will be inhibited until the next START is detected. If the received slave address is acknowledged, zero or more data bytes are received. Software must write the ACK bit after each received byte to ACK or NACK the received byte. The interface exits Slave Receiver Mode after receiving a STOP. Note that the interface will switch to Slave Transmitter Mode if SMB0DAT is written while an active Slave Receiver. Figure 16.10 shows a typical Slave Receiver sequence. Two received data bytes are shown, though any number of bytes may be received. Notice that the `data byte transferred' interrupts occur before the ACK cycle in this mode. Interrupt Received by SMBus Interface Transmitted by SMBus Interface FO Interrupt (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED IN S = START P = STOP A = ACK W = WRITE SLA = Slave Address IO P Interrupt N Page 187 C8051F320/1 16.5.4. Slave Transmitter Mode Advanced Information Figure 16.11. Typical Slave Transmitter Sequence FO A Interrupt RM Data Byte Serial data is transmitted on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START followed by a slave address and direction bit (READ in this case) is received. Upon entering Slave Transmitter Mode, an interrupt is generated and the ACKRQ bit is set. Software responds to the received slave address with an ACK, or ignores the received slave address with a NACK. If the received slave address is ignored, slave interrupts will be inhibited until a START is detected. If the received slave address is acknowledged, data should be written to SMB0DAT to be transmitted. The interface enters Slave Transmitter Mode, and transmits one or more bytes of data. After each byte is transmitted, the master sends an acknowledge bit; if the acknowledge bit is an ACK, SMB0DAT should be written with the next data byte. If the acknowledge bit is a NACK, SMB0DAT should not be written to before SI is cleared (Note: an error condition may be generated if SMB0DAT is written following a received NACK while in Slave Transmitter Mode). The interface exits Slave Transmitter Mode after receiving a STOP. Note that the interface will switch to Slave Receiver Mode if SMB0DAT is not written following a Slave Transmitter interrupt. Figure 16.11 shows a typical Slave Transmitter sequence. Two transmitted data bytes are shown, though any number of bytes may be transmitted. Notice that the `data byte transferred' interrupts occur after the ACK cycle in this mode. Interrupt Received by SMBus Interface Transmitted by SMBus Interface IN S SLA R A Data Byte ED S = START P = STOP N = NACK R = READ SLA = Slave Address AD VA NC Page 188 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. AT N P Interrupt IO Interrupt N Advanced Information 16.6. SMBus Status Decoding C8051F320/1 IO Table 16.4. SMBus Status Decoding VALUES READ MODE ARBLOST STATUS VECTOR ACKRQ CURRENT SMBUS STATE N The current SMBus status can be easily decoded using the SMB0CN register. In the table below, STATUS VECTOR refers to the four upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. Note that the shown response options are only the typical responses; application-specific procedures are allowed as long as they conform to the SMBus specification. Highlighted responses are allowed but do not conform to the SMBus specification. VALUES WRITTEN ACK X X X X X X X X 1 0 0 1 0 1 0 STO 0 0 1 0 1 1 0 0 0 1 1 0 0 0 0 STA 0 1 0 0 0 1 1 0 0 0 1 1 1 0 0 ACK TYPICAL RESPONSE OPTIONS 1110 MASTER TRANSMITTER 0 0 0 0 X A master START was generated. 0 A master data or address byte was transmitted; NACK received. FO 0 0 1 A master data or address byte was transmitted; ACK received. IN 1100 ED VA NC MASTER RECEIVER 1000 1 0 AD A master data byte was received; X ACK requested. (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 RM Load slave address + R/W into SMB0DAT. Set STA to restart transfer. Abort transfer. Load next data byte into SMB0DAT. End transfer with STOP. End transfer with STOP and start another transfer. Send repeated START. Switch to Master Receiver Mode (clear SI without writing new data to SMB0DAT). Acknowledge received byte; Read SMB0DAT. Send NACK to indicate last byte, and send STOP. Send NACK to indicate last byte, and send STOP followed by START. Send ACK followed by repeated START. Send NACK to indicate last byte, and send repeated START. Send ACK and switch to Master Transmitter Mode (write to SMB0DAT before clearing SI). Send NACK and switch to Master Transmitter Mode (write to SMB0DAT before clearing SI). AT Page 189 C8051F320/1 Advanced Information Table 16.4. SMBus Status Decoding VALUES READ MODE ARBLOST STATUS VECTOR ACKRQ VALUES WRITTEN ACK N SLAVE TRANSMITTER 0 0100 0 0 0101 0 0 0 1 X 0 1 X X A slave byte was transmitted; NACK No action required (expecting received. STOP condition). A slave byte was transmitted; ACK received. A Slave byte was transmitted; error detected. A STOP was detected while an addressed Slave Transmitter. Load SMB0DAT with next data byte to transmit. No action required (expecting Master to end transfer). No action required (transfer complete). IO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AT RM FO 1 0 Acknowledge received address. A slave address was received; ACK X Do not acknowledge received requested. address. Acknowledge received address. Do not acknowledge received address. Reschedule failed transfer; do not acknowledge received address. Abort failed transfer. Reschedule failed transfer. No action required (transfer complete/aborted). No action required (transfer complete). Abort transfer. Reschedule failed transfer. Acknowledge received byte; Read SMB0DAT. Do not acknowledge received byte. 0010 1 1 Lost arbitration as master; slave X address received; ACK requested. IN 1 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 SLAVE RECEIVER ED 0010 0 1 1 1 0 1 X X X X Lost arbitration while attempting a repeated START. Lost arbitration while attempting a STOP. A STOP was detected while an addressed slave receiver. Lost arbitration due to a detected STOP. A slave byte was received; ACK requested. VA NC 0001 0 0 1 0 X AD 0000 1 1 X Lost arbitration while transmitting a Abort failed transfer. data byte as master. Reschedule failed transfer. Page 190 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. ACK X X X X 1 0 1 0 0 X X 0 X X X 1 0 0 0 CURRENT SMBUS STATE STO STA TYPICAL RESPONSE OPTIONS Advanced Information 17. UART0 C8051F320/1 Figure 17.1. UART0 Block Diagram SFR Bus Write to SBUF TB8 D CLR Q IN Zero Detector Shift Data SET SBUF (TX Shift) FO TX Crossbar Tx IRQ Send TI Serial Port Interrupt RI Stop Bit Start S0MODE MCE0 REN0 TB80 RB80 TI0 RI0 UART Baud Rate Generator VA NC ED Tx Control Tx Clock SCON0 RM With UART0 interrupts enabled, an interrupt is generated each time a transmit is completed (TI0 is set in SCON0), or a data byte has been received (RI0 is set in SCON0). The UART0 interrupt flags are not cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually by software, allowing software to determine the cause of the UART0 interrupt (transmit complete or receive complete). AT RX UART0 has two associated SFRs: Serial Control Register 0 (SCON0) and Serial Data Buffer 0 (SBUF0). The single SBUF0 location provides access to both transmit and receive registers. Writes to SBUF0 always access the Transmit register. Reads of SBUF0 always access the buffered Receive register; it is not possible to read data from the Transmit register. IO Crossbar N UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in Section "17.1. Enhanced Baud Rate Generation" on page 192). Received data buffering allows UART0 to start reception of a second incoming data byte before software has finished reading the previous data byte. Port I/O Rx IRQ Rx Clock Rx Control Shift 0x1FF RB8 Load SBUF Start AD Read SBUF Input Shift Register (9 bits) Load SBUF0 SBUF (RX Latch) SFR Bus (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 Page 191 C8051F320/1 17.1. Advanced Information Enhanced Baud Rate Generation Figure 17.2. UART0 Baud Rate Logic Timer 1 TL1 Overflow TH1 Start Detected RX Timer Overflow FO RM 2 RX Clock 2 AD Where T1CLK is the frequency of the clock supplied to Timer 1, and T1H is the high byte of Timer 1 (reload value). Timer 1 clock frequency is selected as described in Section "19. Timers" on page 215. A quick reference for typical baud rates and system clock frequencies is given in Table 17.1 through Table 17.6. Note that the internal oscillator may still generate the system clock when the external oscillator is driving Timer 1. VA NC Page 192 ED Timer 1 should be configured for Mode 2, 8-bit auto-reload (see Section "19.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload" on page 217). The Timer 1 reload value should be set so that overflows will occur at two times the desired UART baud rate frequency. Note that Timer 1 may be clocked by one of six sources: SYSCLK, SYSCLK / 4, SYSCLK / 12, SYSCLK / 48, the external oscillator clock / 8, or an external input T1. For any given Timer 1 clock source, the UART0 baud rate is determined by Equation 17.1. Equation 17.1. UART0 Baud Rate T1 CLK 1 -UartBaudRate = ------------------------------ x -( 256 - T1H ) 2 IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. AT UART0 IO TX Clock The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 17.2), which is not user-accessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates. The RX Timer runs when Timer 1 is enabled, and uses the same reload value (TH1). However, an RX Timer reload is forced when a START condition is detected on the RX pin. This allows a receive to begin any time a START is detected, independent of the TX Timer state. N Advanced Information 17.2. Operational Modes C8051F320/1 UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown below. RS-232 RS-232 LEVEL XLTR TX RX C8051Fxxx OR TX TX MCU RX 17.2.1. 8-Bit UART MARK SPACE BIT TIMES VA NC If these conditions are met, the eight bits of data is stored in SBUF0, the stop bit is stored in RB80 and the RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not be set. An interrupt will occur if enabled when either TI0 or RI0 is set. Figure 17.4. 8-Bit UART Timing Diagram D1 D2 D3 D4 D5 D6 D7 STOP BIT START BIT D0 (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD BIT SAMPLING ED Data transmission begins when software writes a data byte to the SBUF0 register. The TI0 Transmit Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to logic 1. After the stop bit is received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met: RI0 must be logic 0, and if MCE0 is logic 1, the stop bit must be logic 1. In the event of a receive data overrun, the first 8 bits received are latched into the SBUF0 receive register and the following overrun data bits are lost. IN 8-Bit UART mode uses a total of 10 bits per data byte: one start bit, eight data bits (LSB first), and one stop bit. Data are transmitted LSB first from the TX0 pin and received at the RX0 pin. On receive, the eight data bits are stored in SBUF0 and the stop bit goes into RB80 (SCON0.2). FO RM RX C8051Fxxx AT Page 193 IO N Figure 17.3. UART Interconnect Diagram C8051F320/1 17.2.2. 9-Bit UART Advanced Information Figure 17.5. 9-Bit UART Timing Diagram MARK SPACE BIT TIMES START BIT D0 D1 D2 D3 D4 D5 D6 D7 D8 STOP BIT BIT SAMPLING AD VA NC Page 194 ED IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM Data transmission begins when an instruction writes a data byte to the SBUF0 register. The TI0 Transmit Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to `1'. After the stop bit is received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met: (1) RI0 must be logic 0, and (2) if MCE0 is logic 1, the 9th bit must be logic 1 (when MCE0 is logic 0, the state of the ninth data bit is unimportant). If these conditions are met, the eight bits of data are stored in SBUF0, the ninth bit is stored in RB80, and the RI0 flag is set to `1'. If the above conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not be set to `1'. A UART0 interrupt will occur if enabled when either TI0 or RI0 is set to `1'. AT IO N 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programmable ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB80 (SCON0.3), which is assigned by user software. It can be assigned the value of the parity flag (bit P in register PSW) for error detection, or used in multiprocessor communications. On receive, the ninth data bit goes into RB80 (SCON0.2) and the stop bit is ignored. Advanced Information 17.3. Multiprocessor Communications C8051F320/1 Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. The master processor can be configured to receive all transmissions or a protocol can be implemented such that the master/slave role is temporarily reversed to enable half-duplex transmission between the original master and slave(s). Master Device RX TX Slave Device RX IN FO Slave Device Figure 17.6. UART Multi-Processor Mode Interconnect Diagram RM TX AT RX Setting the MCE0 bit (SCON.5) of a slave processor configures its UART such that when a stop bit is received, the UART will generate an interrupt only if the ninth bit is logic one (RB80 = 1) signifying an address byte has been received. In the UART interrupt handler, software will compare the received address with the slave's own assigned 8bit address. If the addresses match, the slave will clear its MCE0 bit to enable interrupts on the reception of the following data byte(s). Slaves that weren't addressed leave their MCE0 bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the data. Once the entire message is received, the addressed slave resets its MCE0 bit to ignore all transmissions until it receives the next address byte. Slave Device +5V TX (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED TX RX IO N 9-Bit UART mode supports multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit. When a master processor wants to transmit to one or more slaves, it first sends an address byte to select the target(s). An address byte differs from a data byte in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0. Page 195 C8051F320/1 Advanced Information Figure 17.7. SCON0: Serial Port 0 Control Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 N Bit0 S0MODE - MCE0 REN0 TB80 RB80 TI0 RI0 01000000 SFR Address: Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: AD VA NC S0MODE: Serial Port 0 Operation Mode. This bit selects the UART0 Operation Mode. 0: 8-bit UART with Variable Baud Rate. 1: 9-bit UART with Variable Baud Rate. UNUSED. Read = 1b. Write = don't care. MCE0: Multiprocessor Communication Enable. The function of this bit is dependent on the Serial Port 0 Operation Mode. Mode 0: Checks for valid stop bit. 0: Logic level of stop bit is ignored. 1: RI0 will only be activated if stop bit is logic level 1. Mode 1: Multiprocessor Communications Enable. 0: Logic level of ninth bit is ignored. 1: RI0 is set and an interrupt is generated only when the ninth bit is logic 1. REN0: Receive Enable. This bit enables/disables the UART receiver. 0: UART0 reception disabled. 1: UART0 reception enabled. TB80: Ninth Transmission Bit. The logic level of this bit will be assigned to the ninth transmission bit in 9-bit UART Mode. It is not used in 8-bit UART Mode. Set or cleared by software as required. RB80: Ninth Receive Bit. RB80 is assigned the value of the STOP bit in Mode 0; it is assigned the value of the 9th data bit in Mode 1. TI0: Transmit Interrupt Flag. Set by hardware when a byte of data has been transmitted by UART0 (after the 8th bit in 8-bit UART Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When the UART0 interrupt is enabled, setting this bit causes the CPU to vector to the UART0 interrupt service routine. This bit must be cleared manually by software. RI0: Receive Interrupt Flag. Set to `1' by hardware when a byte of data has been received by UART0 (set at the STOP bit sampling time). When the UART0 interrupt is enabled, setting this bit to `1' causes the CPU to vector to the UART0 interrupt service routine. This bit must be cleared manually by software. Page 196 ED IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM AT IO (bit addressable) 0x98 Advanced Information C8051F320/1 Figure 17.8. SBUF0: Serial (UART0) Port Data Buffer Register R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 N R/W Bit0 Reset Value 00000000 SFR Address: IO 0x99 (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED IN FO RM AT Bits7-0: SBUF0[7:0]: Serial Data Buffer Bits 7-0 (MSB-LSB). This SFR accesses two registers; a transmit shift register and a receive latch register. When data is written to SBUF0, it goes to the transmit shift register and is held for serial transmission. Writing a byte to SBUF0 initiates the transmission. A read of SBUF0 returns the contents of the receive latch. Page 197 C8051F320/1 Advanced Information Table 17.2. Timer Settings for Standard Baud Rates Using an External Oscillator Frequency: 25.0 MHz OscillaTimer 1 SCA1-SCA0 Target Timer Baud Rate tor T1M Reload (pre-scale Baud Rate Clock % Error Divide Value (bps) Source select) Factor (hex) 230400 115200 57600 28800 14400 9600 2400 1200 57600 28800 14400 9600 -0.47% 0.45% -0.01% 0.45% -0.01% 0.15% 0.45% -0.01% -0.47% -0.47% 0.45% 0.15% IN SYSCLK from Internal Osc. VA NC 108 218 434 872 1736 2608 10464 20832 432 864 1744 2608 FO SCA1-SCA0 and T1M bit definitions can be found in Section 19.1. SYSCLK SYSCLK SYSCLK SYSCLK / 4 SYSCLK / 4 EXTCLK / 8 SYSCLK / 48 SYSCLK / 48 EXTCLK / 8 EXTCLK / 8 EXTCLK / 8 EXTCLK / 8 RM 230400 115200 57600 28800 14400 9600 2400 1200 -0.16% -0.16% -0.16% -0.16% -0.16% -0.16% -0.16% -0.16% X = Don't care 52 104 208 416 832 1248 4992 9984 SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK / 4 SYSCLK / 12 SYSCLK /12 SYSCLK / 48 XX XX XX XX 01 00 00 10 IO Table 17.1. Timer Settings for Standard Baud Rates Using The Internal Oscillator Frequency: 12 MHz OscillaTimer 1 SCA1-SCA0 Target Timer tor Baud Rate T1M Reload (pre-scale Baud Rate Clock Divide Value % Error (bps) Source select) Factor (hex) N 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0xE6 0xCC 0x98 0x30 0x98 0xCC 0x30 0x98 SYSCLK from Internal Osc. AT XX XX XX 01 01 11 10 10 11 11 11 11 0xCA 0x93 0x27 0x93 0x27 0x5D 0x93 0x27 0xE5 0xCA 0x93 0x5D AD SYSCLK from External Osc. X = Don't care SCA1-SCA0 Page 198 ED and T1M bit definitions can be found in Section 19.1. DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. Advanced Information C8051F320/1 SCA1-SCA0 and T1M bit definitions can be found in Section 19.1. 230400 115200 57600 28800 14400 9600 2400 1200 230400 115200 57600 28800 14400 9600 VA NC Table 17.4. Timer Settings for Standard Baud Rates Using an External Oscillator Frequency: 18.432 MHz OscillaTimer 1 SCA1-SCA0 Target Timer Baud Rate tor T1M Reload (pre-scale Baud Rate Clock % Error Divide Value (bps) Source select) Factor (hex) 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% X = Don't care ED IN 80 160 320 640 1280 1920 7680 15360 80 160 320 640 1280 1920 FO 230400 115200 57600 28800 14400 9600 2400 1200 230400 115200 57600 28800 14400 9600 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% X = Don't care 96 192 384 768 1536 2304 9216 18432 96 192 384 768 1536 2304 SYSCLK SYSCLK SYSCLK SYSCLK / 12 SYSCLK / 12 SYSCLK / 12 SYSCLK / 48 SYSCLK / 48 EXTCLK / 8 EXTCLK / 8 EXTCLK / 8 EXTCLK / 8 EXTCLK / 8 EXTCLK / 8 XX XX XX 00 00 00 10 10 11 11 11 11 11 11 IO Table 17.3. Timer Settings for Standard Baud Rates Using an External Oscillator Frequency: 22.1184 MHz OscillaTimer 1 SCA1-SCA0 Target Timer tor Baud Rate T1M Reload (pre-scale Baud Rate Clock Divide Value % Error (bps) Source select) Factor (hex) N 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0xD0 0xA0 0x40 0xE0 0xC0 0xA0 0xA0 0x40 0xFA 0xF4 0xE8 0xD0 0xA0 0x70 SYSCLK from External Osc. SYSCLK from Internal Osc. SYSCLK SYSCLK SYSCLK SYSCLK / 4 SYSCLK / 4 SYSCLK / 12 SYSCLK / 48 SYSCLK / 48 EXTCLK / 8 EXTCLK / 8 EXTCLK / 8 EXTCLK / 8 EXTCLK / 8 EXTCLK / 8 RM AT XX XX XX 01 01 00 10 10 11 11 11 11 11 11 0xD8 0xB0 0x60 0xB0 0x60 0xB0 0xB0 0x60 0xFB 0xF6 0xEC 0xD8 0xB0 0x88 SYSCLK from Internal Osc. AD SYSCLK from External Osc. SCA1-SCA0 and T1M bit definitions can be found in Section 19.1. (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 Page 199 C8051F320/1 Advanced Information SCA1-SCA0 and T1M bit definitions can be found in Section 19.1. 230400 115200 57600 28800 14400 9600 2400 1200 230400 115200 57600 28800 14400 9600 VA NC Table 17.6. Timer Settings for Standard Baud Rates Using an External Oscillator Frequency: 3.6864 MHz OscillaTimer 1 SCA1-SCA0 Target Baud Timer tor T1M Reload (pre-scale Baud Rate Rate% Clock Divide Value (bps) Error Source select) Factor (hex) 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% X = Don't care ED IN 16 32 64 128 256 384 1536 3072 16 32 64 128 256 384 FO 230400 115200 57600 28800 14400 9600 2400 1200 230400 115200 57600 28800 14400 9600 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% X = Don't care 48 96 192 384 768 1152 4608 9216 48 96 192 384 768 1152 SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK / 12 SYSCLK / 12 SYSCLK / 12 SYSCLK / 48 EXTCLK / 8 EXTCLK / 8 EXTCLK / 8 EXTCLK / 8 EXTCLK / 8 EXTCLK / 8 XX XX XX XX 00 00 00 10 11 11 11 11 11 11 IO Table 17.5. Timer Settings for Standard Baud Rates Using an External Oscillator Frequency: 11.0592 MHz OscillaTimer 1 SCA1-SCA0 Target Timer tor Baud Rate T1M Reload (pre-scale Baud Rate Clock Divide Value % Error (bps) Source select) Factor (hex) N 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0xE8 0xD0 0xA0 0x40 0xE0 0xD0 0x40 0xA0 0xFD 0xFA 0xF4 0xE8 0xD0 0xB8 SYSCLK from External Osc. SYSCLK from Internal Osc. SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK / 12 SYSCLK / 12 EXTCLK / 8 EXTCLK / 8 EXTCLK / 8 EXTCLK / 8 EXTCLK / 8 EXTCLK / 8 RM AT XX XX XX XX XX XX 00 00 11 11 11 11 11 11 0xF8 0xF0 0xE0 0xC0 0x80 0x40 0xC0 0x80 0xFF 0xFE 0xFC 0xF8 0xF0 0xE8 SYSCLK from Internal Osc. AD SYSCLK from External Osc. SCA1-SCA0 and T1M bit definitions can be found in Section 19.1. Page 200 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. Advanced Information 18. C8051F320/1 ENHANCED SERIAL PERIPHERAL INTERFACE (SPI0) Figure 18.1. SPI Block Diagram SFR Bus SPI0CKR SCR7 SCR6 SCR5 SCR4 SCR3 SCR2 SCR1 SCR0 SYSCLK Clock Divide Logic SPI CONTROL LOGIC Data Path Control Pin Interface Control IN SPI0DAT FO SPI IRQ Tx Data ED RM Pin Control Logic SPI0CFG SPIBSY MSTEN CKPHA CKPOL SLVSEL NSSIN SRMT RXBMT SPI0CN SPIF WCOL MODF RXOVRN NSSMD1 NSSMD0 TXBMT SPIEN MOSI VA NC Transmit Data Buffer AT SCK Shift Register 76543210 Rx Data MISO C R O S S B A R IO The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input to select SPI0 in slave mode, or to disable Master Mode operation in a multi-master environment, avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can also be configured as a chip-select output in master mode, or disabled for 3-wire operation. Additional general purpose port I/O pins can be used to select multiple slave devices in master mode. Receive Data Buffer NSS AD Write SPI0DAT Read SPI0DAT SFR Bus (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 N Port I/O Page 201 C8051F320/1 18.1. Signal Descriptions Advanced Information The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below. 18.1.2. Master In, Slave Out (MISO) 18.1.3. Serial Clock (SCK) 18.1.4. Slave Select (NSS) The function of the slave-select (NSS) signal is dependent on the setting of the NSSMD1 and NSSMD0 bits in the SPI0CN register. There are three possible modes that can be selected with these bits: 1. NSSMD[1:0] = 00: 3-Wire Master or 3-Wire Slave Mode: SPI0 operates in 3-wire mode, and NSS is disabled. When operating as a slave device, SPI0 is always selected in 3-wire mode. Since no select signal is present, SPI0 must be the only slave on the bus in 3-wire mode. This is intended for point-to-point communication between a master and one slave. 2. NSSMD[1:0] = 01: 4-Wire Slave or Multi-Master Mode: SPI0 operates in 4-wire mode, and NSS is enabled as an input. When operating as a slave, NSS selects the SPI0 device. When operating as a master, a 1-to-0 transition of the NSS signal disables the master function of SPI0 so that multiple master devices can be used on the same SPI bus. 3. NSSMD[1:0] = 1x: 4-Wire Master Mode: SPI0 operates in 4-wire mode, and NSS is enabled as an output. The setting of NSSMD0 determines what logic level the NSS pin will output. This configuration should only be used when operating SPI0 as a master device. See Figure 18.2, Figure 18.3, and Figure 18.4 for typical connection diagrams of the various operational modes. Note that the setting of NSSMD bits affects the pinout of the device. When in 3-wire master or 3-wire slave mode, the NSS pin will not be mapped by the crossbar. In all other modes, the NSS signal will be mapped to a pin on the device. See Section "14.1. Priority Crossbar Decoder" on page 127 for general purpose port I/O and crossbar information. AD VA NC Page 202 ED IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO The serial clock (SCK) signal is an output from the master device and an input to slave devices. It is used to synchronize the transfer of data between the master and slave on the MOSI and MISO lines. SPI0 generates this signal when operating as a master. The SCK signal is ignored by a SPI slave when the slave is not selected (NSS = 1) in 4-wire slave mode. RM The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device. It is used to serially transfer data from the slave to the master. This signal is an input when SPI0 is operating as a master and an output when SPI0 is operating as a slave. Data is transferred most-significant bit first. The MISO pin is placed in a high-impedance state when the SPI module is disabled and when the SPI operates in 4-wire mode as a slave that is not selected. When acting as a slave in 3-wire mode, MISO is always driven by the MSB of the shift register. AT IO The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It is used to serially transfer data from the master to the slave. This signal is an output when SPI0 is operating as a master and an input when SPI0 is operating as a slave. Data is transferred most-significant bit first. When configured as a master, MOSI is driven by the MSB of the shift register in both 3- and 4-wire mode. N 18.1.1. Master Out, Slave In (MOSI) Advanced Information 18.2. SPI0 Master Mode Operation C8051F320/1 (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC 4-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 1. In this mode, NSS is configured as an output pin, and can be used as a slave-select signal for a single SPI device. In this mode, the output value of NSS is controlled (in software) with the bit NSSMD0 (SPI0CN.2). Additional slave devices can be addressed using general-purpose I/O pins. Figure 18.4 shows a connection diagram for a master device in 4-wire master mode and two slave devices. ED IN 3-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. In this mode, NSS is not used, and does not get mapped to an external port pin through the crossbar. Any slave devices that must be addressed in this mode should be selected using general-purpose I/O pins. Figure 18.3 shows a connection diagram between a master device in 3-wire master mode and a slave device. FO When configured as a master, SPI0 can operate in one of three different modes: multi-master mode, 3-wire singlemaster mode, and 4-wire single-master mode. The default, multi-master mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In this mode, NSS is an input to the device, and is used to disable the master SPI0 when another master is accessing the bus. When NSS is pulled low in this mode, MSTEN (SPI0CN.6) and SPIEN (SPI0CN.0) are set to 0 to disable the SPI master device, and a Mode Fault is generated (MODF, SPI0CN.5 = 1). Mode Fault will generate an interrupt if enabled. SPI0 must be manually re-enabled in software under these circumstances. In multi-master systems, devices will typically default to being slave devices while they are not acting as the system master device. In multi-master mode, slave devices can be addressed individually (if needed) using generalpurpose I/O pins. Figure 18.2 shows a connection diagram between two master devices in multiple-master mode. RM AT A SPI master device initiates all data transfers on a SPI bus. SPI0 is placed in master mode by setting the Master Enable flag (MSTEN, SPI0CN.6). Writing a byte of data to the SPI0 data register (SPI0DAT) when in master mode writes to the transmit buffer. If the SPI shift register is empty, the byte in the transmit buffer is moved to the shift register, and a data transfer begins. The SPI0 master immediately shifts out the data serially on the MOSI line while providing the serial clock on SCK. The SPIF (SPI0CN.7) flag is set to logic 1 at the end of the transfer. If interrupts are enabled, an interrupt request is generated when the SPIF flag is set. While the SPI0 master transfers data to a slave on the MOSI line, the addressed SPI slave device simultaneously transfers the contents of its shift register to the SPI master on the MISO line in a full-duplex operation. Therefore, the SPIF flag serves as both a transmit-complete and receive-data-ready flag. The data byte received from the slave is transferred MSB-first into the master's shift register. When a byte is fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by reading SPI0DAT. IO N Page 203 C8051F320/1 Advanced Information Figure 18.2. Multiple-Master Mode Connection Diagram NSS GPIO Master Device 1 MOSI SCK GPIO MOSI SCK NSS Master Device 2 Figure 18.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram Master Device MISO MOSI SCK Figure 18.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram Master Device GPIO IN MISO MOSI SCK NSS FO ED VA NC AD Page 204 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. RM MISO MOSI SCK Slave Device MISO MOSI SCK NSS Slave Device MISO MOSI SCK NSS Slave Device AT IO N MISO MISO Advanced Information 18.3. SPI0 Slave Mode Operation C8051F320/1 (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED IN 3-wire slave mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. NSS is not used in this mode, and is not mapped to an external port pin through the crossbar. Since there is no way of uniquely addressing the device in 3-wire slave mode, SPI0 must be the only slave device present on the bus. It is important to note that in 3-wire slave mode there is no external means of resetting the bit counter that determines when a full byte has been received. The bit counter can only be reset by disabling and re-enabling SPI0 with the SPIEN bit. Figure 18.3 shows a connection diagram between a slave device in 3-wire slave mode and a master device. FO RM When configured as a slave, SPI0 can be configured for 4-wire or 3-wire operation. The default, 4-wire slave mode, is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In 4-wire mode, the NSS signal is routed to a port pin and configured as a digital input. SPI0 is enabled when NSS is logic 0, and disabled when NSS is logic 1. The bit counter is reset on a falling edge of NSS. Note that the NSS signal must be driven low at least 2 system clocks before the first active edge of SCK for each byte transfer. Figure 18.4 shows a connection diagram between two slave devices in 4-wire slave mode and a master device. AT When SPI0 is enabled and not configured as a master, it will operate as a SPI slave. As a slave, bytes are shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK signal. A bit counter in the SPI0 logic counts SCK edges. When 8 bits have been shifted through the shift register, the SPIF flag is set to logic 1, and the byte is copied into the receive buffer. Data is read from the receive buffer by reading SPI0DAT. A slave device cannot initiate transfers. Data to be transferred to the master device is pre-loaded into the shift register by writing to SPI0DAT. Writes to SPI0DAT are double-buffered, and are placed in the transmit buffer first. If the shift register is empty, the contents of the transmit buffer will immediately be transferred into the shift register. When the shift register already contains data, the SPI will wait until the byte is transferred before loading it with the transmit buffer's contents. IO N Page 205 C8051F320/1 18.4. SPI0 Interrupt Sources Advanced Information When SPI0 interrupts are enabled, the following four flags will generate an interrupt when they are set to logic 1: Note all of the following bits must be cleared by software. 1. The SPI Interrupt Flag, SPIF (SPI0CN.7) is set to logic 1 at the end of each byte transfer. This flag can be set in all SPI0 modes. 2. The Write Collision Flag, WCOL (SPI0CN.6) is set to logic 1 if a write to SPI0DAT is attempted when the transmit buffer has not been emptied to the SPI shift register. When this occurs, the write to SPI0DAT will be ignored, and the transmit buffer will not be written.This flag can be set in all SPI0 modes. 3. The Mode Fault Flag MODF (SPI0CN.5) is set to logic 1 when SPI0 is configured as a master, and for multi-master mode and the NSS pin is pulled low. When a Mode Fault occurs, the MSTEN and SPIEN bits in SPI0CN are set to logic 0 to disable SPI0 and allow another master device to access the bus. 4. The Receive Overrun Flag RXOVRN (SPI0CN.4) is set to logic 1 when configured as a slave, and a transfer is completed and the receive buffer still holds an unread byte from a previous transfer. The new byte is not transferred to the receive buffer, allowing the previously received data byte to be read. The data byte which caused the overrun is lost. AD VA NC Page 206 ED IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM AT IO N Advanced Information 18.5. Serial Clock Timing C8051F320/1 Figure 18.5. Data/Clock Timing Diagram SCK (CKPOL=0, CKPHA=1) SCK (CKPOL=1, CKPHA=0) SCK (CKPOL=1, CKPHA=1) MISO/MOSI VA NC MSB ED Bit 6 IN Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 SCK (CKPOL=0, CKPHA=0) FO RM The SPI0 Clock Rate Register (SPI0CKR) as shown in Figure 18.8 controls the master mode serial clock frequency. This register is ignored when operating in slave mode. When the SPI is configured as a master, the maximum data transfer rate (bits/sec) is one-half the system clock frequency. When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the system clock frequency, provided that the master issues SCK, NSS (in 4-wire slave mode), and the serial input data synchronously with the system clock. If the master issues SCK, NSS, and the serial input data asynchronously, the maximum data transfer rate (bits/sec) must be less than 1/10 the system clock frequency. In the special case where the master only wants to transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the SPI slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency. This is provided that the master issues SCK, NSS, and the serial input data synchronously with the system clock. AT IO N As shown in Figure 18.5, four combinations of serial clock phase and polarity can be selected using the clock control bits in the SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases (edge used to latch the data). The CKPOL bit (SPI0CFG.4) selects between an active-high or active-low clock. Both master and slave devices must be configured to use the same clock phase and polarity. Note: SPI0 should be disabled (by clearing the SPIEN bit, SPI0CN.0) when changing the clock phase or polarity. Bit 0 NSS (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD Page 207 C8051F320/1 18.6. Advanced Information SPI Special Function Registers SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate Register. The four special function registers related to the operation of the SPI0 Bus are described in the following figures. Figure 18.6. SPI0CFG: SPI0 Configuration Register R R/W R/W R/W R R R IO N R Reset Value SPIBSY Bit7 MSTEN Bit6 CKPHA Bit5 CKPOL Bit4 SLVSEL Bit3 NSSIN Bit2 SRMT Bit1 RXBMT Bit0 00000111 SFR Address: AT 0xA1 Bit 6: Bit 3: Bit 2: Bit 1: Bit 0: In slave mode, data on MOSI is sampled in the center of each data bit. In master mode, data on MISO is sampled one SYSCLK before the end of each data bit, to provide maximum settling time for the slave device. See Table 18.1 for timing parameters. AD VA NC Page 208 ED IN Bit 4: DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO Bit 5: RM Bit 7: SPIBSY: SPI Busy (read-only). This bit is set to logic 1 when a SPI transfer is in progress (Master or slave Mode). MSTEN: Master Mode Enable. 0: Disable master mode. Operate in slave mode. 1: Enable master mode. Operate as a master. CKPHA: SPI0 Clock Phase. This bit controls the SPI0 clock phase. 0: Data centered on first edge of SCK period. 1: Data centered on second edge of SCK period. CKPOL: SPI0 Clock Polarity. This bit controls the SPI0 clock polarity. 0: SCK line low in idle state. 1: SCK line high in idle state. SLVSEL: Slave Selected Flag (read-only). This bit is set to logic 1 whenever the NSS pin is low indicating SPI0 is the selected slave. It is cleared to logic 0 when NSS is high (slave not selected). This bit does not indicate the instantaneous value at the NSS pin, but rather a de-glitched version of the pin input. NSSIN: NSS Instantaneous Pin Input (read-only). This bit mimics the instantaneous value that is present on the NSS port pin at the time that the register is read. This input is not de-glitched. SRMT: Shift Register Empty (Valid in Slave Mode, read-only). This bit will be set to logic 1 when all data has been transferred in/out of the shift register, and there is no new information available to read from the transmit buffer or write to the receive buffer. It returns to logic 0 when a data byte is transferred to the shift register from the transmit buffer or by a transition on SCK. NOTE: SRMT = 1 when in Master Mode. RXBMT: Receive Buffer Empty (Valid in Slave Mode, read-only). This bit will be set to logic 1 when the receive buffer has been read and contains no new information. If there is new information available in the receive buffer that has not been read, this bit will return to logic 0. NOTE: RXBMT = 1 when in Master Mode. Advanced Information C8051F320/1 Figure 18.7. SPI0CN: SPI0 Control Register R/W R/W R/W R/W R/W R/W R R/W Reset Value N Bit0 SPIF Bit7 WCOL Bit6 MODF Bit5 RXOVRN NSSMD1 Bit4 Bit3 NSSMD0 Bit2 TXBMT Bit1 SPIEN 00000110 Bit Addressable SFR Address: IO 0xF8 Bit 5: Bit 4: Bits 3-2: Bit 1: Bit 0: (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED IN FO RM Bit 6: AT Bit 7: SPIF: SPI0 Interrupt Flag. This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts are enabled, setting this bit causes the CPU to vector to the SPI0 interrupt service routine. This bit is not automatically cleared by hardware. It must be cleared by software. WCOL: Write Collision Flag. This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) to indicate a write to the SPI0 data register was attempted while a data transfer was in progress. It must be cleared by software. MODF: Mode Fault Flag. This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when a master mode collision is detected (NSS is low, MSTEN = 1, and NSSMD[1:0] = 01). This bit is not automatically cleared by hardware. It must be cleared by software. RXOVRN: Receive Overrun Flag (Slave Mode only). This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when the receive buffer still holds unread data from a previous transfer and the last bit of the current transfer is shifted into the SPI0 shift register. This bit is not automatically cleared by hardware. It must be cleared by software. NSSMD1-NSSMD0: Slave Select Mode. Selects between the following NSS operation modes: (See Section "18.2. SPI0 Master Mode Operation" on page 203 and Section "18.3. SPI0 Slave Mode Operation" on page 205). 00: 3-Wire Slave or 3-wire Master Mode. NSS signal is not routed to a port pin. 01: 4-Wire Slave or Multi-Master Mode (Default). NSS is always an input to the device. 1x: 4-Wire Single-Master Mode. NSS signal is mapped as an output from the device and will assume the value of NSSMD0. TXBMT: Transmit Buffer Empty. This bit will be set to logic 0 when new data has been written to the transmit buffer. When data in the transmit buffer is transferred to the SPI shift register, this bit will be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer. SPIEN: SPI0 Enable. This bit enables/disables the SPI. 0: SPI disabled. 1: SPI enabled. Page 209 C8051F320/1 Advanced Information Figure 18.8. SPI0CKR: SPI0 Clock Rate Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 N Bit0 SCR7 SCR6 SCR5 SCR4 SCR3 SCR2 SCR1 SCR0 00000000 SFR Address: IO 0xA2 Bits 7-0: Example: If SYSCLK = 2 MHz and SPI0CKR = 0x04, 2000000 f SCK = ------------------------2 x (4 + 1) f SCK = 200kHz AD VA NC Page 210 ED DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. IN FO for 0 <= SPI0CKR <= 255 RM SYSCLK f SCK = -----------------------------------------------2 x ( SPI0CKR + 1 ) AT SCR7-SCR0: SPI0 Clock Rate These bits determine the frequency of the SCK output when the SPI0 module is configured for master mode operation. The SCK clock frequency is a divided version of the system clock, and is given in the following equation, where SYSCLK is the system clock frequency and SPI0CKR is the 8-bit value held in the SPI0CKR register. Advanced Information C8051F320/1 Figure 18.9. SPI0DAT: SPI0 Data Register R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Reset Value N Bit0 00000000 SFR Address: IO 0xA3 Bits 7-0: (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED IN FO RM AT SPI0DAT: SPI0 Transmit and Receive Data. The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to SPI0DAT places the data into the transmit buffer and initiates a transfer when in Master Mode. A read of SPI0DAT returns the contents of the receive buffer. Page 211 C8051F320/1 Advanced Information Figure 18.10. SPI Slave Timing (CKPHA = 0) NSS T T IO SIS SOH N SE CKL T SD T CKH MOSI MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 18.11. SPI Slave Timing (CKPHA = 1) NSS T ED T IN FO T RM SIH T T AT T SD SCK* SCK* VA NC T CKH SE CKL T SIS T SIH AD MOSI MISO T SOH * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Page 212 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. Advanced Information C8051F320/1 Figure 18.12. SPI Master Timing (CKPHA = 0) SCK* T T MCKH MCKL T MIS T MIH MISO MOSI * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 18.13. SPI Master Timing (CKPHA = 1) SCK* T MCKH ED T IN T MCKL MIS FO MISO MOSI * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC RM T MIH AT Page 213 IO N C8051F320/1 Advanced Information Table 18.1. SPI Timing Parameters PARAMETER TSYSCLK DESCRIPTION System Clock Period MIN 40 MAX UNITS ns TSE TSD TCKH TCKL TSIS TSIH TSOH NSS Falling to First SCK Edge (Slave Enable) Last SCK Edge to NSS Rising (Slave Disable) SCK High Time SCK Low Time MOSI Valid to SCK Sample Edge (MOSI Setup) 2*TSYSCLK 2*TSYSCLK 5*TSYSCLK 5*TSYSCLK 2*TSYSCLK 2*TSYSCLK IO 4*TSYSCLK SLAVE MODE TIMING N ns ns ns ns ns ns ns SCK Sample Edge to MOSI Change (MOSI Hold) SCK Shift Edge to MISO Change (MISO Hold) MASTER MODE TIMING TMCKH TMCKL TMIS TMIH SCK High Time SCK Low Time FO RM AT 1*TSYSCLK 1*TSYSCLK 1*TSYSCLK + 20 0 ns ns ns ns MISO Valid to SCK Shift Edge (MOSI Setup) SCK Shift Edge to MISO Change (MISO Hold) See Figure 18.10 and Figure 18.11 for Slave Mode Timing Diagrams. See Figure 18.12 and Figure 18.13 for Master Mode Timing Diagrams. AD Page 214 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. VA NC ED IN Advanced Information 19. TIMERS C8051F320/1 Timers 0 and 1 may be clocked by one of five sources, determined by the Timer Mode Select bits (T1M-T0M) and the Clock Scale bits (SCA1-SCA0). The Clock Scale bits define a pre-scaled clock from which Timer 0 and/or Timer 1 may be clocked (See Figure 19.6 for pre-scaled clock selection). 19.1. Timer 0 and Timer 1 19.1.1. Mode 0: 13-bit Counter/Timer Timer 0 and Timer 1 operate as 13-bit counter/timers in Mode 0. The following describes the configuration and operation of Timer 0. However, both timers operate identically, and Timer 1 is configured in the same manner as described for Timer 0. The TH0 register holds the eight MSBs of the 13-bit counter/timer. TL0 holds the five LSBs in bit positions TL0.4TL0.0. The three upper bits of TL0 (TL0.7-TL0.5) are indeterminate and should be masked out or ignored when reading. As the 13-bit timer register increments and overflows from 0x1FFF (all ones) to 0x0000, the timer overflow flag TF0 (TCON.5) is set and an interrupt will occur if Timer 0 interrupts are enabled. The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to Section "14.1. Priority Crossbar Decoder" on page 127 for information on selecting and configuring external I/O pins). Clearing C/T selects the clock defined by the T0M bit (CKCON.3). When T0M is set, Timer 0 is clocked by the system clock. When T0M is cleared, Timer 0 is clocked by the source selected by the Clock Scale bits in CKCON (see Figure 19.6). (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 Page 215 AD VA NC Each timer is implemented as a 16-bit register accessed as two separate bytes: a low byte (TL0 or TL1) and a high byte (TH0 or TH1). The Counter/Timer Control register (TCON) is used to enable Timer 0 and Timer 1 as well as indicate status. Timer 0 interrupts can be enabled by setting the ET0 bit in the IE register (Section "8.3.5. Interrupt Register Descriptions" on page 61); Timer 1 interrupts can be enabled by setting the ET1 bit in the IE register (Section 8.3.5). Both counter/timers operate in one of four primary modes selected by setting the Mode Select bits T1M1T0M0 in the Counter/Timer Mode register (TMOD). Each timer can be configured independently. Each operating mode is described below. ED IN Timer 0 and Timer 1 may also be operated as counters. When functioning as a counter, a counter/timer register is incremented on each high-to-low transition at the selected input pin (T0 or T1). Events with a frequency of up to onefourth the system clock's frequency can be counted. The input signal need not be periodic, but it should be held at a given level for at least two full system clock cycles to ensure the level is properly sampled. FO Timer 0/1 may then be configured to use this pre-scaled clock signal or the system clock. Timer 2 and Timer 3 may be clocked by the system clock, the system clock divided by 12, or the external oscillator clock source divided by 8. RM AT Timer 0 and Timer 1 Modes: Timer 2 Modes: 13-bit counter/timer 16-bit timer with auto-reload 16-bit counter/timer 8-bit counter/timer with auto-reload Two 8-bit timers with auto-reload Two 8-bit counter/timers (Timer 0 only) Timer 3 Modes: 16-bit timer with auto-reload Two 8-bit timers with auto-reload IO N Each MCU includes four counter/timers: two are 16-bit counter/timers compatible with those found in the standard 8051, and two are 16-bit auto-reload timer for use with the ADC, SMBus, USB (frame measurements), or for general purpose use. These timers can be used to measure time intervals, count external events and generate periodic interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primary modes of operation. Timer 2 and Timer 3 offer 16-bit and split 8-bit timer functionality with auto-reload. C8051F320/1 Advanced Information Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or the input signal /INT0 is active as defined by bit IN0PL in register INT01CF (see Figure 8.13). Setting GATE0 to `1' allows the timer to be controlled by the external input signal /INT0 (see Section "8.3.5. Interrupt Register Descriptions" on page 61), facilitating pulse width measurements. TR0 GATE0 0 X 1 0 1 1 1 1 X = Don't Care /INT0 X X 0 1 Counter/Timer Disabled Enabled Disabled Enabled Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial value before the timer is enabled. TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0. Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The input signal /INT1 is used with Timer 1; the /INT1 polarity is defined by bit IN1PL in register INT01CF (see Figure 8.13). Figure 19.1. T0 Mode 0 Block Diagram CKCON TMOD INT01CF TT 00 MM 10 I N 1 P L I N 1 S L 2 I N 1 S L 1 I N 1 S L 0 I N 0 P L I N 0 S L 2 I N 0 S L 1 I N 0 S L 0 Pre-scaled Clock 0 SYSCLK VA NC ED 1 IN 0 1 TTTTTTSS 3 3 2 2 1 0 CC MMMMMM A A HLHL 10 FO G A T E 1 C / T 1 TTG 11A MM T 10E 0 C / T 0 RM AT TH0 (8 bits) IO TCLK T0 N TCON TL0 (5 bits) TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Interrupt TR0 GATE0 Crossbar /INT0 IN0PL XOR 19.1.2. Mode 1: 16-bit Counter/Timer Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The counter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0. AD Page 216 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. Advanced Information 19.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload C8051F320/1 Figure 19.2. T0 Mode 2 Block Diagram CKCON TTTTTTSS 3 3 2 2 1 0CC MMMMMM A A HLHL 10 G A T E 1 C / T 1 TMOD TTG 11A MM T 10E 0 RM C / T 0 TT 00 MM 10 I N 1 P L I N 1 S L 2 TCLK Pre-scaled Clock 0 0 SYSCLK 1 ED T0 IN 1 FO AT INT01CF I N 1 S L 1 I N 1 S L 0 I N 0 P L I N 0 S L 2 I N 0 S L 1 I N 0 S L 0 Reload Both counter/timers are enabled and configured in Mode 2 in the same manner as Mode 0. Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or when the input signal /INT0 is active as defined by bit IN0PL in register INT01CF (see Section "8.3.2. External Interrupts" on page 59 for details on the external input signals /INT0 and /INT1). IO TCON Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start value. TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from all ones to 0x00, the timer overflow flag TF0 (TCON.5) is set and the counter in TL0 is reloaded from TH0. If Timer 0 interrupts are enabled, an interrupt will occur when the TF0 flag is set. The reload value in TH0 is not changed. TL0 must be initialized to the desired value before enabling the timer for the first count to be correct. When in Mode 2, Timer 1 operates identically to Timer 0. TL0 (8 bits) N TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Interrupt TR0 VA NC Crossbar GATE0 TH0 (8 bits) /INT0 IN0PL XOR (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD Page 217 C8051F320/1 Advanced Information 19.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The counter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0, GATE0 and TF0. TL0 can use either the system clock or an external input signal as its timebase. The TH0 register is restricted to a timer function sourced by the system clock or prescaled clock. TH0 is enabled using the Timer 1 run control bit TR1. TH0 sets the Timer 1 overflow flag TF1 on overflow and thus controls the Timer 1 interrupt. Timer 1 is inactive in Mode 3. When Timer 0 is operating in Mode 3, Timer 1 can be operated in Modes 0, 1 or 2, but cannot be clocked by external signals nor set the TF1 flag and generate an interrupt. However, the Timer 1 overflow can be used to generate baud rates for the SMBus and/or UART, and/or initiate ADC conversions. While Timer 0 is operating in Mode 3, Timer 1 run control is handled through its mode settings. To run Timer 1 while Timer 0 is in Mode 3, set the Timer 1 Mode as 0, 1, or 2. To disable Timer 1, configure it for Mode 3. CKCON TTTTTTS 332210C MMMMMM A HLHL 1 S C A 0 G A T E 1 C / T 1 TMOD T 1 M 1 T 1 M 0 G A T E 0 Pre-scaled Clock 0 FO TR1 RM C / T 0 TT 00 MM 10 Figure 19.3. T0 Mode 3 Block Diagram AT TH0 (8 bits) TL0 (8 bits) IO N TCON SYSCLK 1 0 T0 Crossbar GATE0 /INT0 AD VA NC IN0PL XOR Page 218 ED TR0 IN TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Interrupt Interrupt 1 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. Advanced Information C8051F320/1 Figure 19.4. TCON: Timer Control Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 N Bit0 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00000000 SFR Address: Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD TF1: Timer 1 Overflow Flag. Set by hardware when Timer 1 overflows. This flag can be cleared by software but is automatically cleared when the CPU vectors to the Timer 1 interrupt service routine. 0: No Timer 1 overflow detected. 1: Timer 1 has overflowed. TR1: Timer 1 Run Control. 0: Timer 1 disabled. 1: Timer 1 enabled. TF0: Timer 0 Overflow Flag. Set by hardware when Timer 0 overflows. This flag can be cleared by software but is automatically cleared when the CPU vectors to the Timer 0 interrupt service routine. 0: No Timer 0 overflow detected. 1: Timer 0 has overflowed. TR0: Timer 0 Run Control. 0: Timer 0 disabled. 1: Timer 0 enabled. IE1: External Interrupt 1. This flag is set by hardware when an edge/level of type defined by IT1 is detected. It can be cleared by software but is automatically cleared when the CPU vectors to the External Interrupt 1 service routine if IT1 = 1. When IT1 = 0, this flag is set to `1' when /INT1 is active as defined by bit IN1PL in register INT01CF (see Figure 8.13). IT1: Interrupt 1 Type Select. This bit selects whether the configured /INT1 interrupt will be edge or level sensitive. /INT1 is configured active low or high by the IN1PL bit in the IT01CF register (see Figure 8.13). 0: /INT1 is level triggered. 1: /INT1 is edge triggered. IE0: External Interrupt 0. This flag is set by hardware when an edge/level of type defined by IT0 is detected. It can be cleared by software but is automatically cleared when the CPU vectors to the External Interrupt 0 service routine if IT0 = 1. When IT0 = 0, this flag is set to `1' when /INT0 is active as defined by bit IN0PL in register INT01CF (see Figure 8.13). IT0: Interrupt 0 Type Select. This bit selects whether the configured /INT0 interrupt will be edge or level sensitive. /INT0 is configured active low or high by the IN0PL bit in register IT01CF (see Figure 8.13). 0: /INT0 is level triggered. 1: /INT0 is edge triggered. VA NC ED IN FO RM AT IO (bit addressable) 0x88 Page 219 C8051F320/1 Advanced Information Figure 19.5. TMOD: Timer Mode Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 N Bit0 GATE1 C/T1 T1M1 T1M0 GATE0 C/T0 T0M1 T0M0 00000000 SFR Address: Bit7: Bit6: Bits5-4: Mode 0: 13-bit counter/timer Mode 1: 16-bit counter/timer Mode 2: 8-bit counter/timer with auto-reload Mode 3: Timer 1 inactive Bit3: Bit2: T0M1 0 0 1 1 AD VA NC Bits1-0: GATE0: Timer 0 Gate Control. 0: Timer 0 enabled when TR0 = 1 irrespective of /INT0 logic level. 1: Timer 0 enabled only when TR0 = 1 AND /INT0 is active as defined by bit IN0PL in register INT01CF (see Figure 8.13). C/T0: Counter/Timer Select. 0: Timer Function: Timer 0 incremented by clock defined by T0M bit (CKCON.3). 1: Counter Function: Timer 0 incremented by high-to-low transitions on external input pin (T0). T0M1-T0M0: Timer 0 Mode Select. These bits select the Timer 0 operation mode. T0M0 0 1 0 1 Page 220 ED Mode Mode 0: 13-bit counter/timer Mode 1: 16-bit counter/timer Mode 2: 8-bit counter/timer with auto-reload Mode 3: Two 8-bit counter/timers IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO T1M1 0 0 1 1 T1M0 0 1 0 1 Mode RM GATE1: Timer 1 Gate Control. 0: Timer 1 enabled when TR1 = 1 irrespective of /INT1 logic level. 1: Timer 1 enabled only when TR1 = 1 AND /INT1 is active as defined by bit IN1PL in register INT01CF (see Figure 8.13). C/T1: Counter/Timer 1 Select. 0: Timer Function: Timer 1 incremented by clock defined by T1M bit (CKCON.4). 1: Counter Function: Timer 1 incremented by high-to-low transitions on external input pin (T1). T1M1-T1M0: Timer 1 Mode Select. These bits select the Timer 1 operation mode. AT IO 0x89 Advanced Information C8051F320/1 Figure 19.6. CKCON: Clock Control Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 N Bit0 T3MH T3ML T2MH T2ML T1M T0M SCA1 SCA0 00000000 SFR Address: Bit7: Bit6: Bit5: Bit3: Bits1-0: SCA1 SCA0 Prescaled Clock 0 0 System clock divided by 12 0 1 System clock divided by 4 1 0 System clock divided by 48 1 1 External clock divided by 8 Note: External clock divided by 8 is synchronized with the system clock. (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC Bit2: ED IN Bit4: T3MH: Timer 3 High Byte Clock Select. This bit selects the clock supplied to the Timer 3 high byte if Timer 3 is configured in split 8-bit timer mode. T3MH is ignored if Timer 3 is in any other mode. 0: Timer 3 high byte uses the clock defined by the T3XCLK bit in TMR3CN. 1: Timer 3 high byte uses the system clock. T3ML: Timer 3 Low Byte Clock Select. This bit selects the clock supplied to Timer 3. If Timer 3 is configured in split 8-bit timer mode, this bit selects the clock supplied to the lower 8-bit timer. 0: Timer 3 low byte uses the clock defined by the T3XCLK bit in TMR3CN. 1: Timer 3 low byte uses the system clock. T2MH: Timer 2 High Byte Clock Select. This bit selects the clock supplied to the Timer 2 high byte if Timer 2 is configured in split 8-bit timer mode. T2MH is ignored if Timer 2 is in any other mode. 0: Timer 2 high byte uses the clock defined by the T2XCLK bit in TMR2CN. 1: Timer 2 high byte uses the system clock. T2ML: Timer 2 Low Byte Clock Select. This bit selects the clock supplied to Timer 2. If Timer 2 is configured in split 8-bit timer mode, this bit selects the clock supplied to the lower 8-bit timer. 0: Timer 2 low byte uses the clock defined by the T2XCLK bit in TMR2CN. 1: Timer 2 low byte uses the system clock. T1M: Timer 1 Clock Select. This select the clock source supplied to Timer 1. T1M is ignored when C/T1 is set to logic 1. 0: Timer 1 uses the clock defined by the prescale bits, SCA1-SCA0. 1: Timer 1 uses the system clock. T0M: Timer 0 Clock Select. This bit selects the clock source supplied to Timer 0. T0M is ignored when C/T0 is set to logic 1. 0: Counter/Timer 0 uses the clock defined by the prescale bits, SCA1-SCA0. 1: Counter/Timer 0 uses the system clock. SCA1-SCA0: Timer 0/1 Prescale Bits. These bits control the division of the clock supplied to Timer 0 and/or Timer 1 if configured to use prescaled clock inputs. FO RM AT IO 0x8E Page 221 C8051F320/1 Advanced Information Figure 19.7. TL0: Timer 0 Low Byte R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Reset Value N Bit0 R/W Bit0 R/W Bit0 R/W Bit0 00000000 SFR Address: 0x8A Bits 7-0: TL0: Timer 0 Low Byte. The TL0 register is the low byte of the 16-bit Timer 0. Figure 19.8. TL1: Timer 1 Low Byte R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 RM R/W Bit2 AT R/W Bit1 Reset Value IO 00000000 SFR Address: 0x8B Bits 7-0: TL1: Timer 1 Low Byte. The TL1 register is the low byte of the 16-bit Timer 1. Figure 19.9. TH0: Timer 0 High Byte R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 Reset Value IN FO ED 00000000 SFR Address: 0x8C R/W Bit7 VA NC R/W Bit6 R/W Bit5 Bits 7-0: TH0: Timer 0 High Byte. The TH0 register is the high byte of the 16-bit Timer 0. Figure 19.10. TH1: Timer 1 High Byte R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 Reset Value 00000000 SFR Address: AD 0x8D Bits 7-0: TH1: Timer 1 High Byte. The TH1 register is the high byte of the 16-bit Timer 1. Page 222 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. Advanced Information 19.2. Timer 2 C8051F320/1 Timer 2 is a 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may operate in 16-bit auto-reload mode, (split) 8-bit auto-reload mode, or USB Start-of-Frame (SOF) capture mode. The Timer 2 operation mode is defined by the T2SPLIT (TMR2CN.3) and T2SOF (TMR2CN.4) bits. Timer 2 may be clocked by the system clock, the system clock divided by 12, or the external oscillator source divided by 8. The external clock mode is ideal for real-time clock (RTC) functionality, where the internal oscillator drives the system clock while Timer 2 (and/or the PCA) is clocked by an external precision oscillator. Note that the external oscillator source divided by 8 is synchronized with the system clock. 19.2.1. 16-bit Timer with Auto-Reload Figure 19.11. Timer 2 16-Bit Mode Block Diagram CKCON TTTTTTSS 3 3 2 2 1 0 CC T2XCLK M M M M M M A A HLHL 10 IN TR2 TCLK FO TL2 Overflow RM To SMBus When T2SPLIT = `0' and T2SOF = `0', Timer 2 operates as a 16-bit timer with auto-reload. Timer 2 can be clocked by SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. As the 16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 2 reload registers (TMR2RLH and TMR2RLL) is loaded into the Timer 2 register as shown in Figure 19.11, and the Timer 2 High Byte Overflow Flag (TMR2CN.7) is set. If Timer 2 interrupts are enabled (if IE.5 is set), an interrupt will be generated on each Timer 2 overflow. Additionally, if Timer 2 interrupts are enabled and the TF2LEN bit is set (TMR2CN.5), an interrupt will be generated each time the lower 8 bits (TMR2L) overflow from 0xFF to 0x00. SYSCLK / 12 0 0 ED External Clock / 8 SYSCLK 1 TMR2CN 1 TMR2L TMR2H AT To ADC, SMBus Reload IO TF2H TF2L TF2LEN T2SOF T2SPLIT TR2 T2XCLK N Interrupt VA NC TMR2RLL TMR2RLH (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD Page 223 C8051F320/1 19.2.2. 8-bit Timers with Auto-Reload Advanced Information CKCON T2XCLK TTTTTTSS 3 3 2 2 1 0 CC MMMMMMA A HLHL 10 IN TR2 Figure 19.12. Timer 2 8-Bit Mode Block Diagram FO TCLK The TF2H bit is set when TMR2H overflows from 0xFF to 0x00; the TF2L bit is set when TMR2L overflows from 0xFF to 0x00. When Timer 2 interrupts are enabled (IE.5), an interrupt is generated each time TMR2H overflows. If Timer 2 interrupts are enabled and TF2LEN (TMR2CN.5) is set, an interrupt is generated each time either TMR2L or TMR2H overflows. When TF2LEN is enabled, software must check the TF2H and TF2L flags to determine the source of the Timer 2 interrupt. The TF2H and TF2L interrupt flags are not cleared by hardware and must be manually cleared by software. RM TMR2RLH TMR2H T2MH 0 0 1 T2XCLK 0 1 X TMR2H Clock Source SYSCLK / 12 External Clock / 8 SYSCLK T2ML 0 0 1 AT T2XCLK 0 1 X TMR2CN T2XCLK Reload External Clock / 8 1 ED SYSCLK / 12 0 0 IO To SMBus TF2H TF2L TF2LEN T2SOF T2SPLIT TR2 Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. The Timer 2 Clock Select bits (T2MH and T2ML in CKCON) select either SYSCLK or the clock defined by the Timer 2 External Clock Select bit (T2XCLK in TMR2CN), as follows: TMR2L Clock Source SYSCLK / 12 External Clock / 8 SYSCLK N When T2SPLIT = `1' and T2SOF = `0', Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers operate in auto-reload mode as shown in Figure 19.12. TMR2RLL holds the reload value for TMR2L; TMR2RLH holds the reload value for TMR2H. The TR2 bit in TMR2CN handles the run control for TMR2H. TMR2L is always running when configured for 8-bit Mode. Interrupt 1 VA NC TMR2RLL Reload SYSCLK 1 TCLK TMR2L To ADC, SMBus 0 AD Page 224 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. Advanced Information 19.2.3. USB Start-of-Frame Capture C8051F320/1 Figure 19.13. Timer 2 SOF Capture Mode (T2SPLIT = `0') TMR2CN T F 2 H T F 2 L TTTT F22R 2SS2 LOP EFL N I T T 2 X C L K CKCON TTTTTTSS 3 3 2 2 1 0 CC MMMMMM A A HLHL 10 SYSCLK / 12 0 0 TR2 TCLK RM TL2 Overflow AT To SMBus IO External Clock / 8 SYSCLK 1 1 USB Start-of-Frame (SOF) TMR2L TMR2H FO Capture TMR2RLL TMR2RLH IN Enable Interrupt Figure 19.14. Timer 2 SOF Capture Mode (T2SPLIT = `1') T F 2 H T F 2 L VA NC TMR2CN TTTT F22R 2SS2 LOP EFL NI T T 2 X C L K ED When T2SPLIT = `1', the Timer 2 registers (TMR2H and TMR2L) act as two 8-bit counters. Each counter counts up independently and overflows from 0xFF to 0x00. Each time a USB SOF is received, the contents of the Timer 2 registers are latched into the Timer 2 Reload registers (TMR2RLH and TMR2RLL). A Timer 2 interrupt is generated if enabled. CKCON TTTTTTSS 3 3 2 2 1 0CC MMMMMM A A HLHL 10 TMR2RLH Capture N Enable USB Start-of-Frame (SOF) When T2SOF = `1', Timer 2 operates in USB Start-of-Frame (SOF) capture mode. When T2SPLIT = `0', Timer 2 counts up and overflows from 0xFFFF to 0x0000. Each time a USB SOF is received, the contents of the Timer 2 registers (TMR2H:TMR2L) are latched into the Timer 2 Reload registers (TMR2RLH:TMR2RLL). A Timer 2 interrupt is generated if enabled. This mode can be used to calibrate the system clock or external oscillator against the known USB host SOF clock. To ADC, SMBus Interrupt SYSCLK / 12 0 0 TCLK TR2 1 Capture AD External Clock / 8 1 TMR2H To SMBus TMR2RLL SYSCLK 1 TCLK 0 TMR2L To ADC, SMBus (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 Page 225 C8051F320/1 Advanced Information Figure 19.15. TMR2CN: Timer 2 Control Register TF2H Bit7 TF2L Bit6 TF2LEN Bit5 T2SOF Bit4 T2SPLIT Bit3 TR2 Bit2 Bit1 N Bit0 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value T2XCLK 00000000 SFR Address: IO (bit addressable) 0xC8 Bit7: Bit4: Bit3: Bit2: Bit1: Bit0: AD VA NC Page 226 ED IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO Bit5: RM Bit6: TF2H: Timer 2 High Byte Overflow Flag. Set by hardware when the Timer 2 high byte overflows from 0xFF to 0x00. In 16 bit mode, this will occur when Timer 2 overflows from 0xFFFF to 0x0000. When the Timer 2 interrupt is enabled, setting this bit causes the CPU to vector to the Timer 2 interrupt service routine. TF2H is not automatically cleared by hardware and must be cleared by software. TF2L: Timer 2 Low Byte Overflow Flag. Set by hardware when the Timer 2 low byte overflows from 0xFF to 0x00. When this bit is set, an interrupt will be generated if TF2LEN is set and Timer 2 interrupts are enabled. TF2L will set when the low byte overflows regardless of the Timer 2 mode. This bit is not automatically cleared by hardware. TF2LEN: Timer 2 Low Byte Interrupt Enable. This bit enables/disables Timer 2 Low Byte interrupts. If TF2LEN is set and Timer 2 interrupts are enabled, an interrupt will be generated when the low byte of Timer 2 overflows. 0: Timer 2 Low Byte interrupts disabled. 1: Timer 2 Low Byte interrupts enabled. T2SOF: Timer 2 Start-Of-Frame Capture Enable 0: SOF Capture disabled. 1: SOF Capture enabled. Each time a USB SOF is received, the contents of the Timer 2 registers (TMR2H and TMR2L) are latched into the Timer 2 reload registers (TMR2RLH and TMR2RLH), and a Timer 2 interrupt is generated (if enabled). T2SPLIT: Timer 2 Split Mode Enable. When this bit is set, Timer 2 operates as two 8-bit timers with auto-reload. 0: Timer 2 operates in 16-bit auto-reload mode. 1: Timer 2 operates as two 8-bit auto-reload timers. TR2: Timer 2 Run Control. This bit enables/disables Timer 2. In 8-bit mode, this bit enables/disables TMR2H only; TMR2L is always enabled in this mode. 0: Timer 2 disabled. 1: Timer 2 enabled. UNUSED. Read = 0b. Write = don't care. T2XCLK: Timer 2 External Clock Select. This bit selects the external clock source for Timer 2. If Timer 2 is in 8-bit mode, this bit selects the external oscillator clock source for both timer bytes. However, the Timer 2 Clock Select bits (T2MH and T2ML in register CKCON) may still be used to select between the external clock and the system clock for either timer. 0: Timer 2 external clock selection is the system clock divided by 12. 1: Timer 2 external clock selection is the external clock divided by 8. Note that the external oscillator source divided by 8 is synchronized with the system clock. AT Advanced Information C8051F320/1 Figure 19.16. TMR2RLL: Timer 2 Reload Register Low Byte R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Reset Value N Bit0 R/W Bit0 R/W Bit0 R/W Bit0 00000000 SFR Address: Bits 7-0: Figure 19.17. TMR2RLH: Timer 2 Reload Register High Byte R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 RM R/W Bit2 AT R/W Bit1 R/W Bit1 R/W Bit1 TMR2RLL: Timer 2 Reload Register Low Byte. TMR2RLL holds the low byte of the reload value for Timer 2 when operating in auto-reload mode, or the captured value of the TMR2L register in capture mode. IO 0xCA Reset Value 00000000 SFR Address: Bits 7-0: Figure 19.18. TMR2L: Timer 2 Low Byte R/W Bit7 R/W Bit6 R/W Bit5 ED R/W Bit4 IN TMR2RLH: Timer 2 Reload Register High Byte. The TMR2RLH holds the high byte of the reload value for Timer 2 when operating in auto-reload mode, or the captured value of the TMR2H register in capture mode. FO 0xCB R/W Bit3 R/W Bit2 Reset Value 00000000 SFR Address: 0xCC Bits 7-0: TMR2L: Timer 2 Low Byte. In 16-bit mode, the TMR2L register contains the low byte of the 16-bit Timer 2. In 8-bit mode, TMR2L contains the 8-bit low byte timer value. AD R/W Bit7 VA NC R/W Bit6 R/W Bit5 Figure 19.19. TMR2H Timer 2 High Byte R/W Bit4 R/W Bit3 R/W Bit2 Reset Value 00000000 SFR Address: 0xCD Bits 7-0: TMR2H: Timer 2 High Byte. In 16-bit mode, the TMR2H register contains the high byte of the 16-bit Timer 2. In 8-bit mode, TMR2H contains the 8-bit high byte timer value. (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 Page 227 C8051F320/1 19.3. Timer 3 Advanced Information Timer 3 is a 16-bit timer formed by two 8-bit SFRs: TMR3L (low byte) and TMR3H (high byte). Timer 3 may operate in 16-bit auto-reload mode, (split) 8-bit auto-reload mode, or USB Start-of-Frame (SOF) capture mode. The Timer 3 operation mode is defined by the T3SPLIT (TMR3CN.3) and T3SOF (TMR2CN.4) bits. Timer 3 may be clocked by the system clock, the system clock divided by 12, or the external oscillator source divided by 8. The external clock mode is ideal for real-time clock (RTC) functionality, where the internal oscillator drives the system clock while Timer 3 (and/or the PCA) is clocked by an external precision oscillator. Note that the external oscillator source divided by 8 is synchronized with the system clock. 19.3.1. 16-bit Timer with Auto-Reload Figure 19.20. Timer 3 16-Bit Mode Block Diagram CKCON T3XCLK TTTTTTSS 3 3 2 2 1 0CC MMMMMM A A HLHL 10 IN TCLK FO TMR3L RM TMR3H When T3SPLIT (TMR3CN.3) is zero, Timer 3 operates as a 16-bit timer with auto-reload. Timer 3 can be clocked by SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. As the 16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 3 reload registers (TMR3RLH and TM3RLL) is loaded into the Timer 3 register as shown in Figure 19.11, and the Timer 3 High Byte Overflow Flag (TMR3CN.7) is set. If Timer 3 interrupts are enabled (if IE.5 is set), an interrupt will be generated on each Timer 3 overflow. Additionally, if Timer 3 interrupts are enabled and the TF3LEN bit is set (TMR3CN.5), an interrupt will be generated each time the lower 8 bits (TMR3L) overflow from 0xFF to 0x00. SYSCLK / 12 0 0 TR3 ED AT To ADC IO TF3H TF3L TF3LEN T3SOF T3SPLIT TR3 T3XCLK N External Clock / 8 SYSCLK 1 VA NC TMR3RLL TMR3RLH Reload AD Page 228 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. TMR3CN 1 Interrupt Advanced Information 19.3.2. 8-bit Timers with Auto-Reload C8051F320/1 T3XCLK TTTTTTSS 3 3 2 2 1 0CC MMMMMM A A HLHL 10 IN CKCON TR3 Figure 19.21. Timer 3 8-Bit Mode Block Diagram FO TCLK The TF3H bit is set when TMR3H overflows from 0xFF to 0x00; the TF3L bit is set when TMR3L overflows from 0xFF to 0x00. When Timer 3 interrupts are enabled (IE.5), an interrupt is generated each time TMR3H overflows. If Timer 3 interrupts are enabled and TF3LEN (TMR3CN.5) is set, an interrupt is generated each time either TMR3L or TMR3H overflows. When TF3LEN is enabled, software must check the TF3H and TF3L flags to determine the source of the Timer 3 interrupt. The TF3H and TF3L interrupt flags are not cleared by hardware and must be manually cleared by software. ED SYSCLK / 12 0 RM TMR3RLH TMR3H T3MH 0 0 1 T3XCLK 0 1 X TMR3H Clock Source SYSCLK / 12 External Clock / 8 SYSCLK T3ML 0 0 1 AT T3XCLK 0 1 X To ADC TMR3CN TF3H TF3L TF3LEN T3SOF T3SPLIT TR3 T3XCLK Reload 0 External Clock / 8 1 IO Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. The Timer 3 Clock Select bits (T3MH and T3ML in CKCON) select either SYSCLK or the clock defined by the Timer 3 External Clock Select bit (T3XCLK in TMR3CN), as follows: TMR3L Clock Source SYSCLK / 12 External Clock / 8 SYSCLK N When T3SPLIT is set, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit timers operate in autoreload mode as shown in Figure 19.12. TMR3RLL holds the reload value for TMR3L; TMR3RLH holds the reload value for TMR3H. The TR3 bit in TMR3CN handles the run control for TMR3H. TMR3L is always running when configured for 8-bit Mode. Interrupt 1 VA NC TMR3RLL Reload SYSCLK 1 TCLK TMR3L 0 (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD Page 229 C8051F320/1 19.3.3. USB Start-of-Frame Capture Advanced Information Figure 19.22. Timer 3 SOF Capture Mode (T3SPLIT = `0') TMR3CN T F 3 H T F 3 L TTTT F33R 3SS3 L OP EFL N I T T 3 X C L K CKCON TTTTTTSS 3 3 2 2 1 0 CC MMMMMM A A HLHL 10 SYSCLK / 12 0 0 TR3 TCLK RM TMR3L Interrupt AT TMR3H To ADC External Clock / 8 SYSCLK 1 1 USB Start-of-Frame (SOF) FO Capture Enable TMR3RLL TMR3RLH Figure 19.23. Timer 3 SOF Capture Mode (T3SPLIT = `1') TMR3CN T F 3 H T F 3 L TTTT F33R 3SS3 LOP EFL N I T VA NC T 3 X C L K ED When T3SPLIT = `1', the Timer 3 registers (TMR3H and TMR3L) act as two 8-bit counters. Each counter counts up independently and overflows from 0xFF to 0x00. Each time a USB SOF is received, the contents of the Timer 3 registers are latched into the Timer 3 Reload registers (TMR3RLH and TMR3RLL). A Timer 3 interrupt is generated if enabled. IN CKCON TTTTTTSS 3 3 2 2 1 0 CC MMMMMMA A HLHL 10 TMR3RLH Capture IO N Enable When T3SOF = `1', Timer 3 operates in USB Start-of-Frame (SOF) capture mode. When T3SPLIT = `0', Timer 3 counts up and overflows from 0xFFFF to 0x0000. Each time a USB SOF is received, the contents of the Timer 3 registers (TMR3H:TMR3L) are latched into the Timer 3 Reload registers (TMR3RLH:TMR3RLL). A Timer 3 interrupt is generated if enabled. This mode can be used to calibrate the system clock or external oscillator against the known USB host SOF clock. Interrupt SYSCLK / 12 0 0 TCLK TR3 1 Capture AD External Clock / 8 1 TMR3H To ADC TMR3RLL SYSCLK USB Start-of-Frame (SOF) 1 TCLK 0 TMR3L Page 230 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. Advanced Information C8051F320/1 Figure 19.24. TMR3CN: Timer 3 Control Register TF3H Bit7 TF3L Bit6 TF3LEN Bit5 T3SOF Bit4 T3SPLIT Bit3 TR3 Bit2 Bit1 N Bit0 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value T3XCLK 00000000 SFR Address: IO 0x91 Bit7: Bit4: Bit3: Bit2: Bit1: Bit0: (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED IN FO Bit5: RM Bit6: TF3H: Timer 3 High Byte Overflow Flag. Set by hardware when the Timer 3 high byte overflows from 0xFF to 0x00. In 16 bit mode, this will occur when Timer 3 overflows from 0xFFFF to 0x0000. When the Timer 3 interrupt is enabled, setting this bit causes the CPU to vector to the Timer 3 interrupt service routine. TF3H is not automatically cleared by hardware and must be cleared by software. TF3L: Timer 3 Low Byte Overflow Flag. Set by hardware when the Timer 3 low byte overflows from 0xFF to 0x00. When this bit is set, an interrupt will be generated if TF3LEN is set and Timer 3 interrupts are enabled. TF3L will set when the low byte overflows regardless of the Timer 3 mode. This bit is not automatically cleared by hardware. TF3LEN: Timer 3 Low Byte Interrupt Enable. This bit enables/disables Timer 3 Low Byte interrupts. If TF3LEN is set and Timer 3 interrupts are enabled, an interrupt will be generated when the low byte of Timer 3 overflows. This bit should be cleared when operating Timer 3 in 16-bit mode. 0: Timer 3 Low Byte interrupts disabled. 1: Timer 3 Low Byte interrupts enabled. T3SOF: Timer 3 Start-Of-Frame Capture Enable 0: SOF Capture disabled. 1: SOF Capture enabled. Each time a USB SOF is received, the contents of the Timer 3 registers (TMR3H and TMR3L) are latched into the Timer3 reload registers (TMR3RLH and TMR3RLH), and a Timer 3 interrupt is generated (if enabled). T3SPLIT: Timer 3 Split Mode Enable. When this bit is set, Timer 3 operates as two 8-bit timers with auto-reload. 0: Timer 3 operates in 16-bit auto-reload mode. 1: Timer 3 operates as two 8-bit auto-reload timers. TR3: Timer 3 Run Control. This bit enables/disables Timer 3. In 8-bit mode, this bit enables/disables TMR3H only; TMR3L is always enabled in this mode. 0: Timer 3 disabled. 1: Timer 3 enabled. UNUSED. Read = 0b. Write = don't care. T3XCLK: Timer 3 External Clock Select. This bit selects the external clock source for Timer 3. If Timer 3 is in 8-bit mode, this bit selects the external oscillator clock source for both timer bytes. However, the Timer 3 Clock Select bits (T3MH and T3ML in register CKCON) may still be used to select between the external clock and the system clock for either timer. 0: Timer 3 external clock selection is the system clock divided by 12. 1: Timer 3 external clock selection is the external clock divided by 8. Note that the external oscillator source divided by 8 is synchronized with the system clock. AT Page 231 C8051F320/1 Advanced Information Figure 19.25. TMR3RLL: Timer 3 Reload Register Low Byte R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Reset Value N Bit0 R/W Bit0 R/W Bit0 R/W Bit0 00000000 SFR Address: Bits 7-0: Figure 19.26. TMR3RLH: Timer 3 Reload Register High Byte R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 RM R/W Bit2 AT R/W Bit1 R/W Bit1 R/W Bit1 TMR3RLL: Timer 3 Reload Register Low Byte. TMR3RLL holds the low byte of the reload value for Timer 3 when operating in auto-reload mode, or the captured value of the TMR3L register when operating in capture mode. IO 0x92 Reset Value 00000000 SFR Address: Bits 7-0: Figure 19.27. TMR3L: Timer 3 Low Byte R/W Bit7 R/W Bit6 R/W Bit5 ED R/W Bit4 IN TMR3RLH: Timer 3 Reload Register High Byte. The TMR3RLH holds the high byte of the reload value for Timer 3 when operating in auto-reload mode, or the captured value of the TMR3H register when operating in capture mode. FO 0x93 R/W Bit3 R/W Bit2 Reset Value 00000000 SFR Address: 0x94 Bits 7-0: TMR3L: Timer 3 Low Byte. In 16-bit mode, the TMR3L register contains the low byte of the 16-bit Timer 3. In 8-bit mode, TMR3L contains the 8-bit low byte timer value. AD R/W Bit7 VA NC R/W Bit6 R/W Bit5 Figure 19.28. TMR3H Timer 3 High Byte R/W Bit4 R/W Bit3 R/W Bit2 Reset Value 00000000 SFR Address: 0x95 Bits 7-0: TMR3H: Timer 3 High Byte. In 16-bit mode, the TMR3H register contains the high byte of the 16-bit Timer 3. In 8-bit mode, TMR3H contains the 8-bit high byte timer value. Page 232 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. Advanced Information 20. C8051F320/1 PROGRAMMABLE COUNTER ARRAY (PCA0) Important Note: The PCA Module 4 may be used as a watchdog timer (WDT), and is enabled in this mode following a system reset. Access to certain PCA registers is restricted while WDT mode is enabled. See Section 20.3 for details. Figure 20.1. PCA Block Diagram SYSCLK/12 SYSCLK/4 Timer 0 Overflow ECI SYSCLK External Clock/8 PCA CLOCK MUX VA NC Capture/Compare Module 0 ED Capture/Compare Module 1 IN CEX1 16-Bit Counter/Timer FO CEX2 Capture/Compare Module 2 RM The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer and five 16-bit capture/compare modules. Each capture/compare module has its own associated I/O line (CEXn) which is routed through the Crossbar to Port I/O when enabled (See Section "14.1. Priority Crossbar Decoder" on page 127 for details on configuring the Crossbar). The counter/timer is driven by a programmable timebase that can select between six sources: system clock, system clock divided by four, system clock divided by twelve, the external oscillator clock source divided by 8, Timer 0 overflow, or an external clock signal on the ECI input pin. Each capture/compare module may be configured to operate independently in one of six modes: Edge-Triggered Capture, Software Timer, HighSpeed Output, Frequency Output, 8-Bit PWM, or 16-Bit PWM (each mode is described in Section "20.2. Capture/ Compare Modules" on page 235). The external oscillator clock option is ideal for real-time clock (RTC) functionality, allowing the PCA to be clocked by a precision external oscillator while the internal oscillator drives the system clock. The PCA is configured and controlled through the system controller's Special Function Registers. The PCA block diagram is shown in Figure 20.1 AT CEX3 Capture/Compare Module 3 IO N Capture/Compare Module 4 / WDT CEX0 CEX4 AD (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 ECI Crossbar Port I/O Page 233 C8051F320/1 20.1. PCA Counter/Timer Advanced Information Table 20.1. PCA Timebase Input Options CPS2 0 0 0 0 1 1 External oscillator source divided by 8 External oscillator source divided by 8 is synchronized with the system clock. IDLE CWW I DD DTL LEC K VA NC PCA0MD C P S 2 CCE PPC SSF 10 CC FR ED Figure 20.2. PCA Counter/Timer Block Diagram PCA0CN CC CC FF 43 CC CC FF 21 C C F 0 PCA0L read IN 0 1 CPS1 0 0 1 1 0 0 CPS0 0 1 0 1 0 1 Timebase System clock divided by 12 System clock divided by 4 Timer 0 overflow High-to-low transitions on ECI (max rate = system clock divided by 4) System clock FO RM PCA0H When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD is set to logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in PCA0MD to logic 1 enables the CF flag to generate an interrupt request. The CF bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by software (Note: PCA0 interrupts must be globally enabled before CF interrupts are recognized. PCA0 interrupts are globally enabled by setting the EA bit (IE.7) and the EPCA0 bit in EIE1 to logic 1). Clearing the CIDL bit in the PCA0MD register allows the PCA to continue normal operation while the CPU is in Idle mode. Snapshot Register SYSCLK/12 SYSCLK/4 AD 000 001 010 011 Timer 0 Overflow ECI AT PCA0L IO To SFR Bus Overflow To PCA Modules The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte (MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches the value of PCA0H into a "snapshot" register; the following PCA0H read accesses this "snapshot" register. Reading the PCA0L Register first guarantees an accurate reading of the entire 16-bit PCA0 counter. Reading PCA0H or PCA0L does not disturb the counter operation. The CPS2-CPS0 bits in the PCA0MD register select the timebase for the counter/timer as shown in Table 20.1. SYSCLK 100 101 External Clock/8 Page 234 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. N CF To PCA Interrupt System Advanced Information 20.2. Capture/Compare Modules C8051F320/1 Table 20.2. PCA0CPM Register Settings for PCA Capture/Compare Modules PWM16 ECOM X X X X X X 0 1 X X X CAPP CAPN 1 0 1 0 1 1 0 0 0 0 0 MAT 0 0 0 1 1 X X X TOG 0 0 0 0 1 1 0 0 PWM ECCF 0 0 0 X Operation Mode Capture triggered by positive edge on CEXn Capture triggered by negative edge on CEXn Capture triggered by transition on CEXn Software Timer High Speed Output Frequency Output 8-Bit Pulse Width Modulator 16-Bit Pulse Width Modulator Figure 20.3. PCA Interrupt Block Diagram (for n = 0 to 4) PCA0CPMn P ECCMT P E WC A A A OWC MOPP TGMC 1 MP N n n n F 6nnn n n PCA Counter/ Timer Overflow PCA0CN CC FR CCCCC CCCCC FFFFF 43210 VA NC ECCF0 ED PCA0MD C WW I DD DTL L EC K CCCE PPPC SSSF 210 IN 0 1 1 0 1 0 1 0 1 0 1 0 X = Don't Care FO 0 0 1 1 1 RM X X X X X X X AT EPCA0 Table 20.2 summarizes the bit settings in the PCA0CPMn registers used to select the PCA capture/compare module's operating modes. Setting the ECCFn bit in a PCA0CPMn register enables the module's CCFn interrupt. Note: PCA0 interrupts must be globally enabled before individual CCFn interrupts are recognized. PCA0 interrupts are globally enabled by setting the EA bit and the EPCA0 bit to logic 1. See Figure 20.3 for details on the PCA interrupt configuration. IO 0 1 PCA Module 0 (CCF0) 0 1 N EA Each module can be configured to operate independently in one of six operation modes: Edge-triggered Capture, Software Timer, High Speed Output, Frequency Output, 8-Bit Pulse Width Modulator, or 16-Bit Pulse Width Modulator. Each module has Special Function Registers (SFRs) associated with it in the CIP-51 system controller. These registers are used to exchange data with a module and configure the module's mode of operation. 0 1 AD ECCF1 0 1 Interrupt Priority Decoder PCA Module 1 (CCF1) ECCF2 0 1 PCA Module 2 (CCF2) ECCF3 PCA Module 3 (CCF3) ECCF4 0 1 PCA Module 4 (CCF4) 0 1 (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 Page 235 C8051F320/1 20.2.1. Edge-triggered Capture Mode Advanced Information Figure 20.4. PCA Capture Mode Diagram PCA0CPMn x0 FO 000x P ECCMT P E WC A A AOWC MOPP TGMC 1 MPN n n n F 6nnn n n (to CCFn) RM CC FR 0 1 PCA0CN CCCCC CCCCC FFFFF 43210 AT PCA Timebase In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA counter/timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transition that triggers the capture: low-tohigh transition (positive edge), high-to-low transition (negative edge), or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by software. If both CAPPn and CAPNn bits are set to logic 1, then the state of the Port pin associated with CEXn can be read directly to determine whether a rising-edge or falling-edge caused the capture. PCA Interrupt IO Capture PCA0CPLn N PCA0CPHn 0 1 Port I/O Crossbar CEXn IN PCA0L PCA0H Note: The CEXn input signal must remain high or low for at least 2 system clock cycles to be recognized by the hardware. AD Page 236 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. VA NC ED Advanced Information 20.2.2. Software Timer (Compare) Mode C8051F320/1 Figure 20.5. PCA Software Timer Mode Diagram Write to PCA0CPLn Reset Write to PCA0CPHn 0 ENB RM FO PCA0CPLn PCA0CPHn AT Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit to `0'; writing to PCA0CPHn sets ECOMn to `1'. IO Match N CC FR 0 1 In Software Timer mode, the PCA counter/timer value is compared to the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by software. Setting the ECOMn and MATn bits in the PCA0CPMn register enables Software Timer mode. ENB PCA Interrupt 1 PCA0CPMn P ECCMT P E WC A A AOWC MOPP TGMC 1 MP N n n n F 6nnn n n x 00 00x Enable PCA0CN CCCCC CCCCC FFFFF 43210 IN PCA Timebase 16-bit Comparator ED PCA0L PCA0H (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC Page 237 C8051F320/1 20.2.3. High Speed Output Mode Advanced Information In High Speed Output mode, a module's associated CEXn pin is toggled each time a match occurs between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn) Setting the TOGn, MATn, and ECOMn bits in the PCA0CPMn register enables the High-Speed Output mode. Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit to `0'; writing to PCA0CPHn sets ECOMn to `1'. Figure 20.6. PCA High Speed Output Mode Diagram Write to PCA0CPLn Reset Write to PCA0CPHn 0 ENB PCA0CPMn ENB 1 x 00 0x RM FO Match P ECCMT P E WC A A AOWC MOPP TGMC 1 MP N n n n F n 6nnn n PCA0CPLn PCA0CPHn IN Enable 16-bit Comparator ED Toggle 0 CEXn 1 AT PCA Interrupt PCA0CN CC FR CCCCC CCCCC FFFFF 43210 0 1 TOGn IO N Crossbar Port I/O PCA Timebase PCA0L PCA0H AD Page 238 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. VA NC Advanced Information 20.2.4. Frequency Output Mode C8051F320/1 Frequency Output Mode produces a programmable-frequency square wave on the module's associated CEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the output is toggled. The frequency of the square wave is then defined by Equation 20.1. Equation 20.1. Square Wave Frequency Output F PCA F CEXn = ---------------------------------------2 x PCA0CPHn Figure 20.7. PCA Frequency Output Mode Write to PCA0CPLn Reset Write to PCA0CPHn 0 ENB PCA0CPMn ENB 1 IN Enable P ECCMT P E WC A A A OWC MOPP TGMC 1 MP N n n n F 6nnn n n x 000 x PCA0CPLn FO RM Adder Enable Where FPCA is the frequency of the clock selected by the CPS2-0 bits in the PCA mode register, PCA0MD. The lower byte of the capture/compare module is compared to the PCA counter low byte; on a match, CEXn is toggled and the offset held in the high byte is added to the matched value in PCA0CPLn. Frequency Output Mode is enabled by setting the ECOMn, TOGn, and PWMn bits in the PCA0CPMn register. 8-bit Adder AT TOGn Toggle match 0 CEXn 1 8-bit Comparator IO PCA0CPHn Crossbar Port I/O ED PCA Timebase PCA0L (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC N Page 239 C8051F320/1 Advanced Information 20.2.5. 8-Bit Pulse Width Modulator Mode Each module can be used independently to generate a pulse width modulated (PWM) output on its associated CEXn pin. The frequency of the output is dependent on the timebase for the PCA counter/timer. The duty cycle of the PWM output signal is varied using the module's PCA0CPLn capture/compare register. When the value in the low byte of the PCA counter/timer (PCA0L) is equal to the value in PCA0CPLn, the output on the CEXn pin will be set. When the count value in PCA0L overflows, the CEXn output will be reset (see Figure 20.8). Also, when the counter/timer low byte (PCA0L) overflows from 0xFF to 0x00, PCA0CPLn is reloaded automatically with the value stored in the module's capture/compare high byte (PCA0CPHn) without software intervention. Setting the ECOMn and PWMn bits in the PCA0CPMn register enables 8-Bit Pulse Width Modulator mode. The duty cycle for 8-Bit PWM Mode is given by Equation 20.2. Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit to `0'; writing to PCA0CPHn sets ECOMn to `1'. Equation 20.2. 8-Bit PWM Duty Cycle ( 256 - PCA0CPHn ) DutyCycle = -------------------------------------------------256 Using Equation 20.2, the largest duty cycle is 100% (PCA0CPHn = 0), and the smallest duty cycle is 0.39% (PCA0CPHn = 0xFF). A 0% duty cycle may be generated by clearing the ECOMn bit to `0'. Figure 20.8. PCA 8-Bit PWM Mode Diagram Write to PCA0CPLn Reset Write to PCA0CPHn 0 ENB ENB 1 PCA0CPMn P ECCMT P E WC A A A OWC MOPP TGMC 1 MP N n n n F 6nnn n n 0 00x0 x ED VA NC IN Enable PCA0CPHn PCA0CPLn 8-bit Comparator FO RM match AT S SET Q IO CEXn Crossbar N Port I/O R CLR Q PCA Timebase PCA0L Overflow AD Page 240 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. Advanced Information 20.2.6. 16-Bit Pulse Width Modulator Mode C8051F320/1 Equation 20.3. 16-Bit PWM Duty Cycle Figure 20.9. PCA 16-Bit PWM Mode Write to PCA0CPLn Reset Write to PCA0CPHn 0 ENB ENB 1 PCA0CPMn P ECCMT P E WC A A AOWC MOPP TGMC 1 MPN n n n F 6nnn n n 1 00x0 x ED IN PCA0CPHn PCA0CPLn Enable FO Using Equation 20.3, the largest duty cycle is 100% (PCA0CPn = 0), and the smallest duty cycle is 0.0015% (PCA0CPn = 0xFFFF). A 0% duty cycle may be generated by clearing the ECOMn bit to `0'. RM match ( 65536 - PCA0CPn ) DutyCycle = ---------------------------------------------------65536 16-bit Comparator AT S SET Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit to `0'; writing to PCA0CPHn sets ECOMn to `1'. Q IO CEXn A PCA module may also be operated in 16-Bit PWM mode. In this mode, the 16-bit capture/compare module defines the number of PCA clocks for the low time of the PWM signal. When the PCA counter matches the module contents, the output on CEXn is asserted high; when the counter overflows, CEXn is asserted low. To output a varying duty cycle, new value writes should be synchronized with PCA CCFn match interrupts. 16-Bit PWM Mode is enabled by setting the ECOMn, PWMn, and PWM16n bits in the PCA0CPMn register. For a varying duty cycle, match interrupts should be enabled (ECCFn = 1 AND MATn = 1) to help synchronize the capture/compare register writes. The duty cycle for 16-Bit PWM Mode is given by Equation 20.3. N Crossbar Port I/O VA NC R CLR Q PCA Timebase PCA0H PCA0L Overflow (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD Page 241 C8051F320/1 20.3. Watchdog Timer Mode Advanced Information A programmable watchdog timer (WDT) function is available through the PCA Module 4. The WDT is used to generate a reset if the time between writes to the WDT update register (PCA0CPH4) exceed a specified limit. The WDT can be configured and enabled/disabled as needed by software. With the WDTE and/or WDLCK bits set to `1' in the PCA0MD register, Module 4 operates as a watchdog timer (WDT). The Module 4 high byte is compared to the PCA counter high byte; the Module 4 low byte holds the offset to be used when WDT updates are performed. The Watchdog Timer is enabled on reset. Writes to some PCA registers are restricted while the Watchdog Timer is enabled. 20.3.1. Watchdog Timer Operation While the WDT is enabled: * * * * * * PCA counter is forced on. Writes to PCA0L and PCA0H are not allowed. PCA clock source bits (CPS2-CPS0) are frozen. PCA Idle control bit (CIDL) is frozen. Module 4 is forced into Watchdog Timer mode. Writes to the Module 4 mode register (PCA0CPM4) are disabled. PCA0MD CWW I DD DT L LEC K CCCE PPPC SSSF 210 ED Figure 20.10. PCA Module 4 with Watchdog Timer Enabled VA NC IN While the WDT is enabled, writes to the CR bit will not change the PCA counter state; the counter will run until the WDT is disabled. The PCA counter run control (CR) will read zero if the WDT is enabled but user software has not enabled the PCA counter. If a match occurs between PCA0CPH4 and PCA0H while the WDT is enabled, a reset will be generated. To prevent a WDT reset, the WDT may be updated with a write of any value to PCA0CPH4. Upon a PCA0CPH4 write, PCA0H plus the offset held in PCA0CPL4 is loaded into PCA0CPH4 (See Figure 20.10). FO PCA0CPH4 8-bit Comparator RM Match Reset PCA0L Overflow Enable AD PCA0CPL4 8-bit Adder Adder Enable PCA0H Write to PCA0CPH4 Page 242 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. AT IO N Advanced Information C8051F320/1 Note that the 8-bit offset held in PCA0CPH4 is compared to the upper byte of the 16-bit PCA counter. This offset value is the number of PCA0L overflows before a reset. Up to 256 PCA clocks may pass before the first PCA0L overflow occurs, depending on the value of the PCA0L when the update is performed. The total offset is then given (in PCA clocks) by Equation 20.4, where PCA0L is the value of the PCA0L register at the time of the update. Equation 20.4. Watchdog Timer Offset in PCA Clocks Offset = ( 256 x PCA0CPL4 ) + ( 256 - PCA0L ) The WDT reset is generated when PCA0L overflows while there is a match between PCA0CPH4 and PCA0H. Software may force a WDT reset by writing a `1' to the CCF4 flag (PCA0CN.4) while the WDT is enabled. To configure the WDT, perform the following tasks: 1. 2. 3. 4. 5. 6. Table 20.3. Watchdog Timer Timeout Intervals System Clock (Hz) 12,000,000 12,000,000 12,000,000 18,432,000 18,432,000 18,432,000 11,059,200 11,059,200 11,059,200 4,000,000 4,000,000 4,000,000 32,000 32,000 32,000 PCA0CPL4 255 128 32 255 128 32 255 128 32 255 128 32 255 128 32 Timeout Interval (ms) 65.5 33.0 8.4 42.7 21.5 5.5 71.1 35.8 9.2 196.6 99.1 25.3 24,576.0 12,384.0 3,168.0 (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC Assumes SYSCLK / 12 as the PCA clock source, and a PCA0L value of 0x00 at the update time. Internal oscillator reset frequency. ED The WDT is enabled following any reset. The PCA0 counter clock defaults to the system clock divided by 12, PCA0L defaults to 0x00, and PCA0CPL4 defaults to 0x00. Using Equation 20.4, this results in a WDT timeout interval of 256 system clock cycles. Table 20.3 lists some example timeout intervals for typical system clocks. IN The PCA clock source and Idle mode select cannot be changed while the WDT is enabled. The watchdog timer is enabled by setting the WDTE or WDLCK bits in the PCA0MD register. When WDLCK is set, the WDT cannot be disabled until the next system reset. If WDLCK is not set, the WDT is disabled by clearing the WDTE bit. FO Disable the WDT by writing a `0' to the WDTE bit. Select the desired PCA clock source (with the CPS2-CPS0 bits). Load PCA0CPL4 with the desired WDT update offset value. Configure the PCA Idle mode (set CIDL if the WDT should be suspended while the CPU is in Idle mode). Enable the WDT by setting the WDTE bit to `1'. (optional) Lock the WDT (prevent WDT disable until the next system reset) by setting the WDLCK bit to `1'. RM AT 20.3.2. Watchdog Timer Usage IO N Page 243 C8051F320/1 20.4. Advanced Information Register Descriptions for PCA Figure 20.11. PCA0CN: PCA Control Register R/W R/W R/W R/W R/W R/W R/W Following are detailed descriptions of the special function registers related to the operation of the PCA. N R/W Bit0 Reset Value CF Bit7 CR Bit6 Bit5 CCF4 Bit4 CCF3 Bit3 CCF2 Bit2 CCF1 Bit1 IO CCF0 00000000 SFR Address: (bit addressable) 0xD8 Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: AD VA NC CF: PCA Counter/Timer Overflow Flag. Set by hardware when the PCA Counter/Timer overflows from 0xFFFF to 0x0000. When the Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software. CR: PCA Counter/Timer Run Control. This bit enables/disables the PCA Counter/Timer. 0: PCA Counter/Timer disabled. 1: PCA Counter/Timer enabled. UNUSED. Read = 0b, Write = don't care. CCF4: PCA Module 4 Capture/Compare Flag. This bit is set by hardware when a match or capture occurs. When the CCF4 interrupt is enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software. CCF3: PCA Module 3 Capture/Compare Flag. This bit is set by hardware when a match or capture occurs. When the CCF3 interrupt is enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software. CCF2: PCA Module 2 Capture/Compare Flag. This bit is set by hardware when a match or capture occurs. When the CCF2 interrupt is enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software. CCF1: PCA Module 1 Capture/Compare Flag. This bit is set by hardware when a match or capture occurs. When the CCF1 interrupt is enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software. CCF0: PCA Module 0 Capture/Compare Flag. This bit is set by hardware when a match or capture occurs. When the CCF0 interrupt is enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software. Page 244 ED IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM AT Advanced Information C8051F320/1 Figure 20.12. PCA0MD: PCA Mode Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 N Bit0 CIDL WDTE WDLCK - CPS2 CPS1 CPS0 ECF 01000000 SFR Address: Bit7: Bit6: Bit5: Bit4: Bits3-1: 0 1 1 1 1 1 0 0 1 1 VA NC External oscillator source divided by 8 is synchronized with the system clock. Bit0: (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD ECF: PCA Counter/Timer Overflow Interrupt Enable. This bit sets the masking of the PCA Counter/Timer Overflow (CF) interrupt. 0: Disable the CF interrupt. 1: Enable a PCA Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is set. ED CPS2 0 0 0 CPS1 0 0 1 CPS0 0 1 0 1 0 1 0 1 IN CIDL: PCA Counter/Timer Idle Control. Specifies PCA behavior when CPU is in Idle Mode. 0: PCA continues to function normally while the system controller is in Idle Mode. 1: PCA operation is suspended while the system controller is in Idle Mode. WDTE: Watchdog Timer Enable If this bit is set, PCA Module 4 is used as the watchdog timer. 0: Watchdog Timer disabled. 1: PCA Module 4 enabled as Watchdog Timer. WDLCK: Watchdog Timer Lock This bit enables and locks the Watchdog Timer. When WDLCK is set to `1', the Watchdog Timer may not be disabled until the next system reset. 0: Watchdog Timer unlocked. 1: Watchdog Timer enabled and locked. UNUSED. Read = 0b, Write = don't care. CPS2-CPS0: PCA Counter/Timer Pulse Select. These bits select the timebase source for the PCA counter. Timebase System clock divided by 12 System clock divided by 4 Timer 0 overflow High-to-low transitions on ECI (max rate = system clock divided by 4) System clock External clock divided by 8 Reserved Reserved FO RM AT IO 0xD9 Page 245 C8051F320/1 Advanced Information Figure 20.13. PCA0CPMn: PCA Capture/Compare Mode Registers R/W R/W R/W R/W R/W R/W R/W R/W Reset Value PWM16n Bit7 ECOMn Bit6 CAPPn Bit5 CAPNn Bit4 MATn Bit3 TOGn Bit2 PWMn Bit1 EECFn 00000000 SFR Address: 0xDA, 0xDB, 0xDC, 0xDD, 0xDE PCA0CPMn Address: Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit0: AD Bit1: PWM16n: 16-bit Pulse Width Modulation Enable. This bit selects 16-bit mode when Pulse Width Modulation mode is enabled (PWMn = 1). 0: 8-bit PWM selected. 1: 16-bit PWM selected. ECOMn: Comparator Function Enable. This bit enables/disables the comparator function for PCA module n. 0: Disabled. 1: Enabled. CAPPn: Capture Positive Function Enable. This bit enables/disables the positive edge capture for PCA module n. 0: Disabled. 1: Enabled. CAPNn: Capture Negative Function Enable. This bit enables/disables the negative edge capture for PCA module n. 0: Disabled. 1: Enabled. MATn: Match Function Enable. This bit enables/disables the match function for PCA module n. When enabled, matches of the PCA counter with a module's capture/compare register cause the CCFn bit in PCA0MD register to be set to logic 1. 0: Disabled. 1: Enabled. TOGn: Toggle Function Enable. This bit enables/disables the toggle function for PCA module n. When enabled, matches of the PCA counter with a module's capture/compare register cause the logic level on the CEXn pin to toggle. If the PWMn bit is also set to logic 1, the module operates in Frequency Output Mode. 0: Disabled. 1: Enabled. PWMn: Pulse Width Modulation Mode Enable. This bit enables/disables the PWM function for PCA module n. When enabled, a pulse width modulated signal is output on the CEXn pin. 8-bit PWM is used if PWM16n is cleared; 16-bit mode is used if PWM16n is set to logic 1. If the TOGn bit is also set, the module operates in Frequency Output Mode. 0: Disabled. 1: Enabled. ECCFn: Capture/Compare Flag Interrupt Enable. This bit sets the masking of the Capture/Compare Flag (CCFn) interrupt. 0: Disable CCFn interrupts. 1: Enable a Capture/Compare Flag interrupt request when CCFn is set. VA NC Page 246 ED IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM AT PCA0CPM0 = 0xDA (n = 0), PCA0CPM1 = 0xDB (n = 1), PCA0CPM2 = 0xDC (n = 2), PCA0CPM3 = 0xDD (n = 3), PCA0CPM4 = 0xDE (n = 4) IO N Bit0 Advanced Information C8051F320/1 Figure 20.14. PCA0L: PCA Counter/Timer Low Byte R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Reset Value 00000000 N Bit0 R/W Bit0 SFR Address: 0xF9 Bits 7-0: PCA0L: PCA Counter/Timer Low Byte. The PCA0L register holds the low byte (LSB) of the 16-bit PCA Counter/Timer. Figure 20.15. PCA0H: PCA Counter/Timer High Byte R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 Reset Value RM AT IO 00000000 SFR Address: 0xFA (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED IN FO Bits 7-0: PCA0H: PCA Counter/Timer High Byte. The PCA0H register holds the high byte (MSB) of the 16-bit PCA Counter/Timer. Page 247 C8051F320/1 Advanced Information Figure 20.16. PCA0CPLn: PCA Capture Module Low Byte R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Reset Value N Bit0 R/W Bit0 00000000 SFR Address: 0xFB, 0xE9, 0xEB, 0xED, 0xFD Bits7-0: R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 FO R/W Bit3 Figure 20.17. PCA0CPHn: PCA Capture Module High Byte R/W Bit2 R/W Bit1 Reset Value RM PCA0CPLn: PCA Capture Module Low Byte. The PCA0CPLn register holds the low byte (LSB) of the 16-bit capture module n. AT PCA0CPLn Address: PCA0CPL0 = 0xFB (n = 0), PCA0CPL1 = 0xE9 (n = 1), PCA0CPL2 = 0xEB (n = 2), PCA0CPL3 = 0xED (n = 3), PCA0CPL4 = 0xFD (n = 4) IO 00000000 SFR Address: 0xFC, 0xEA, 0xEC,0xEE, 0xFE AD Page 248 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. VA NC Bits7-0: PCA0CPHn: PCA Capture Module High Byte. The PCA0CPHn register holds the high byte (MSB) of the 16-bit capture module n. ED PCA0CPHn Address: PCA0CPH0 = 0xFC (n = 0), PCA0CPH1 = 0xEA (n = 1), PCA0CPH2 = 0xEC (n = 2), PCA0CPH3 = 0xEE (n = 3), PCA0CPH4 = 0xFE (n = 4) IN Advanced Information 21. C2 INTERFACE C8051F320/1 21.1. C2 Interface Registers Figure 21.1. C2ADD: C2 Address Register RM Bit2 Bit2 AT Bit1 Bit1 The following describes the C2 registers necessary to perform FLASH programming and boundary scan functions through the C2 interface. All C2 registers are accessed through the C2 interface as described in the C2 Interface Specification. IO N Bit0 Bit0 C8051F320/1 devices include an on-chip Cygnal 2-Wire (C2) debug interface to allow FLASH programming, boundary scan functions, and in-system debugging with the production part installed in the end application. The C2 interface operates similar to JTAG, where the functionality of the three JTAG data signals (TDI, TDO, TMS) is mapped into one bi-directional C2 data signal (C2D). See the C2 Interface Specification for details on the C2 protocol. Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bits7-0: The C2ADD register is accessed via the C2 interface to select the target Data register for C2 Data Read and Data Write commands. Address 0x00 0x01 0x02 0xB4 Description Selects the Device ID register (DEVICEID) for Data Read instructions Selects the Revision ID register (REVID) for Data Read instructions Selects the C2 FLASH Programming Control register (FPCTL) for Data Read/Write instructions Selects the C2 FLASH Programming Data register (FPDAT) for Data Read/Write instructions VA NC Figure 21.2. DEVICEID: C2 Device ID Register (update) Reset Value ED IN FO 00001001 Bit4 Bit3 C2 Address: Bit7 Bit6 Bit5 0x00 (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD This read-only register returns the 8-bit device ID: 0x09 (C8051F320/1). Page 249 C8051F320/1 Advanced Information Figure 21.3. REVID: C2 Revision ID Register N Bit0 Bit0 Bit0 Reset Value 00000001 C2 Address: IO Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 0x01 This read-only register returns the 8-bit revision ID: 0x00 (Revision B). Figure 21.4. FPCTL: C2 FLASH Programming Control Register RM Bit2 AT Bit1 Bit1 Reset Value 00000000 C2 Address: Bit7 Bit6 Bit5 Bit4 Bit3 Bits7-0 Figure 21.5. FPDAT: C2 FLASH Programming Data Register Reset Value ED IN FPCTL: FLASH Programming Control Register. This register is used to enable FLASH programming via the C2 interface. To enable C2 FLASH programming, the following codes must be written in order: 0x02, 0x01. Note that once C2 FLASH programming is enabled, a system reset must be issued to resume normal operation. FO 0x02 Bit7 VA NC 00000000 Bit3 Bit2 C2 Address: Bit6 Bit5 Bit4 0xB4 Bits7-0: FPDAT: C2 FLASH Programming Data Register. This register is used to pass FLASH commands, addresses, and data during C2 FLASH accesses. Valid commands are listed below. Code 0x06 0x07 0x08 0x03 Command FLASH Block Read FLASH Block Write FLASH Page Erase Device Erase AD Page 250 DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. Advanced Information 21.2. C2 Pin Sharing C8051F320/1 Figure 21.6. Typical C2 Pin Sharing /Reset (a) Input (b) Output (c) RM FO The configuration in Figure 21.6 assumes the following: 1. 2. The user input (b) cannot change state while the target device is halted. The /RST pin on the target device is used as an input only. (c) 2002 Cygnal Integrated Products, Inc. DS010-0.9 NOV02 AD VA NC ED Additional resistors may be necessary depending on the specific application. IN AT C2CK C2D C8051Fxxx IO The C2 protocol allows the C2 pins to be shared with user functions so that in-system debugging, FLASH programming, and boundary scan functions may be performed. This is possible because C2 communication is typically performed when the device is in the halt state, where all on-chip peripherals and user software are stalled. In this halted state, the C2 interface can safely `borrow' the C2CK and C2D pins. In most applications, external resistors are required to isolate C2 interface traffic from the user application. A typical isolation configuration is shown in Figure 21.6. N Page 251 C8051F320/1 Disclaimers Advanced Information CYGNAL INTEGRATED PRODUCTS 4301 Westbank Drive Suite B-100 Austin, TX 78746 www.cygnal.com AD VA NC Page 252 ED IN DS010-0.9 NOV02 (c) 2002 Cygnal Integrated Products, Inc. FO RM CIP-51 is a trademark of Cygnal Integrated Products, Inc. MCS-51 and SMBus are trademarks of Intel Corporation. I2C is a trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc. AT Right to make changes: Cygnal Integrated Products reserves the right to make changes, without notice, in the products, including circuits and/or software, described or contained herein in order to improve design and/or performance. Cygnal Integrated Products assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work infringement, unless otherwise specified. IO N Life support: These products are not designed for use in life support appliances or systems where malfunction of these products can reasonably be expected to result in personal injury. Cygnal Integrated Products customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Cygnal Integrated Products for any damages resulting from such applications. |
Price & Availability of C8051F320
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |